Cypress STK22C48 Hardware STORE Cycle, Switching Waveform

STK22C48

Document Number: 001-51000 Rev. ** Page 11 of 14

Hardware STORE Cycle

Parameter Alt Description STK22C48 Unit

Min Max

tDHSB [13, 16] tRECOVER, tHHQX Hardware STORE High to Inhibit Off 700 ns

tPHSB tHLHX Hardware STORE Pulse Width 15 ns

tHLBL Hardware STORE Low to STORE Busy 300 ns

Switching Waveform

Figure 12. Hardware STORE Cycle

Note

16.tDHSB is only applicable after tSTORE is complete.

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Contents

Main 16 Kbit (2K x 8) AutoStore nvSRAM Features Functional Description Logic Block Diagram STK22C48 Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC 28-SOIC Top View Device Operation SRAM Read SRAM Write AutoStore Operation AutoStore Inhibit mode STK22C48 Hardware STORE (HSB) Operation Hardware RECALL (Power Up) Data Protection Noise Considerations Preventing Store Best Practices Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Conditions STK22C48 AC Switching Characteristics SRAM Read Cycle Switching Waveforms SRAM Write Cycle Switching Waveforms Figure 10. SRAM Write Cycle 2: CE Controlled [10, 11] AutoStore or Power Up RECALL Switching Waveform Hardware STORE Cycle Switching Waveform Ordering Information STK22C48 - N F 45 I TR Package Diagrams Figure 14. 28-Pin (330 mil) SOIC (51-85058) Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions