Delta Tau 4AX-603625-XUXX BOARD CONFIGURATION

UMAC-CPCI Turbo CPU Board Hardware Reference Manual

Board Configuration 3

BOARD CONFIGURATION

The base version of the UMAC-CPCI Turbo CPU board provides a 1-slot 3U-format Eurocard board

with:

• 80 MHz DSP56303 CPU (120 MHz PMAC equivalent)

• 128k x 24 SRAM compiled/assembled program memory (Opt. 5C0)

• 128k x 24 SRAM user data memory (Opt. 5C0)

• 1M x 8 flash memory for user backup & firmware (Opt. 5C0)

• Latest released firmware version

• RS-232/422 serial interface, available both on front-panel DB-9 connector and on backside field-

wiring connector

• Backplane Compact UBUS expansion connector for communication to servo and I/O accessory

boards

• Backside field-wiring connector

The UMAC-CPCI Turbo CPU board comes standard only with an RS-232/422 serial interface. The

Option 1 family provides faster interfaces for high-speed communications – Universal Serial Bus (USB),

Ethernet, or the link to the CPCI bus through a “bridge” daughter board.

• Option 1: On-board 10-Base-T TCP/IP Ethernet interface. The key added components are U67 and

U32.

• Option 1A: On-board 12 Mbit/sec USB interface. The key added component is U67.

• Option 1B: Solder-side stack connectors to CPCI-bridge daughter board. This option should only be

ordered when the bridge board is to be installed on the left side of the CPU board, so the CPU board

is in the leftmost slot of the Compact UBUS backplane, and the bridge board is in the rightmost slot

of the Compact PCI bus backplane.

With either the Option 1 Ethernet interface, or the Option 1A USB interface, communications throughput

can be increased through the use of dual-ported RAM, which provides a bank of memory that can be

directly accessed by both the UMAC-CPCI Turbo CPU and the communications microcontroller.

• Option 2: 32k x 16 bank of on-board dual-ported RAM (requires Option 1 or 1A) in component U56.

The various versions of Option 5 provide different CPU speeds and main memory sizes on the piggyback

CPU board. Only one Option 5xx may be selected for the board.

The CPU is a DSP563xx IC as component U1. It is currently available only as an 80 MHz or 100 MHz

device (with computational power equivalent to a 120 MHz or 150 MHz non-Turbo PMAC, respectively),

but higher speed versions may become available.

The compiled/assembled-program (“P”) memory SRAM ICs are located in U14, U15, and U16. These

ICs form the active memory for the firmware, compiled PLCs, and user-written phase/servo algorithms.

These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger

512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.

The user-data memory (“X/Y”) SRAM ICs are locat ed in U11, U12, and U13. These ICs form the active

memory for user motion programs, uncompiled PLC programs, and user tables and buffers. These can be

128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k x 8 ICs

(for a 512k x 24 bank), fitting in the full footprint.