RTC - 72421 / 72423
Examples of connection to
When connecting the
8085/MCS48,51 | 8085/MCS48,51 |
| |||
AD3 | A3 | AD3 |
| A3 | |
AD2 | A2 | AD2 | Latch | A2 | |
AD1 | A1 | AD1 | A1 | ||
| |||||
AD0 | A0 | AD0 |
| A0 | |
| D3 |
|
| D3 | |
| D2 |
|
| D2 | |
Upper address bus | D1 | Upper address bus |
| D1 | |
Decoder | D0 | Decoder |
| D0 | |
IO/M | CS0 | IO/M |
| CS0 | |
ALE | ALE | ALE |
| ALE | |
RD | RD | RD |
| RD | |
WR | WR | WR |
| WR |
The resistors on the RD and WR lines are not necessary if the CPU does not have a HALT or HOLD state.
2. Connection to Z80 or compatible CPUZ80, SMC84C00AC |
| |
A3 |
| A3 |
A2 |
| A2 |
A1 |
| A1 |
A0 |
| A0 |
D3 |
| D3 |
D2 |
| D2 |
D1 |
| D1 |
D0 |
| D0 |
Upper address bus |
| CS0 |
| Decoder | |
IORQ or |
| |
| ALE | |
MEMRQ |
| |
|
| |
RD |
| RD |
|
| |
WR |
| WR |
|
|
*Select IORQ or MEMRQ depending on whether the RTC maps I/O or memory of the CPU.
3. Connection to68 series MPU |
| |
A3 |
| A3 |
A2 |
| A2 |
A1 |
| A1 |
A0 |
| A0 |
D3 |
| D3 |
D2 |
| D2 |
D1 |
| D1 |
D0 |
| D0 |
Upper address bus | Decoder | CS0 |
|
| ALE |
R/W |
| RD |
|
| |
E |
| WR |
Page - 18 | MQ - 162 - 03 |