14. CHARACTERISTIC MEASURING CIRCUITS

zDescription of tPHL

Input: VDD

VDD=VDET+ +1.0V *3

VDD=0.9V

Output: VOUT

tPHL

VDD=VDET+ +1.0V

VOUT=VDD(0.9V)

 

50%

VSS

*3: VDET+ indicates the actual release voltage. VDET+=VDET-×1.05 (Typ.)

(1)For CMOS output

tPHL provides the timeframe ranging from a time when the pulse voltage (VDET+)+1.0V → 0.9V is applied to VDD, to a time when the output voltage reaches VDD/2.

(2)Nch open drain output

tPHL provides the timeframe ranging from a time when the pulse voltage (VDET+)+1.0V → 0.9V is

applied to VDD, to a time when the output voltage reaches VDD/2.

The output pin is pulled up with 470kΩ resistance and VDD power for measurement.

zDescription of td

Input: VDD

VDD=VDET+ +1.0V

VDD=0.9V

td

Output: VOUT

VOUT= 100 %

50%

VSS

(1)For CMOS output

td provides the timeframe ranging from a time when the pulse voltage 0.9V → (VDET+)+1.0V is applied to VDD, to a time when the output voltage reaches VDD/2.

(2)For Nch open drain output

td provides the timeframe ranging from a time when the pulse voltage 0.9V → (VDET+)+1.0V is

applied to VDD, to a time when the output voltage reaches VDD/2.

The output pin is pulled up with 470kΩ resistance and VDD power for measurement.

S1F77B01 Technical Manual (Rev.1.3)

EPSON

11