Epson S1F77B01 5.BLOCK DIAGRAM, 5.BLOCK DIAGRAM

5.BLOCK DIAGRAM

5.BLOCK DIAGRAM

zCMOS output

VDD

VREF

DS*

Delay circuit

VOUT

VSS

zNch open drain output

VDD

VREF

DS*

Delay circuit

VOUT

VSS

Note: SOT23 package product only; otherwise, a product with DS pin set to NC The DS pin must be fixed to “LOW” outside the IC.

2 EPSON S1F77B01 Technical Manual (Rev.1.3)