Fujitsu CM71-00101-5E - page 310

286
INDEX
Interrupt Level Mask Register (ILM: Bit 20 to bit 16)
............................................................19
LD (Load Word Data in Memory to Program Status
Register)............................................. 157
Note on PS Register............................................22
Overview of the Multiplication/Division Register
............................................................29
Overview of the Table Base Register....................23
Precautions Related to the Table Base Register..... 24
STILM (Set Immediate Data to Interrupt Level Mask
Register)............................................. 240
System Condition Code Register (SCR: Bit 10 to
bit 08).. ................................................20
Table Base Register Configuration....................... 24
Table Base Register Functions............................. 24
Register Bypassing
Register Bypassing............................................. 56
Register Hazards
Overview of Register Hazards............................. 56
Remainder
DIV2 (Correction when Remainder is 0).............134
DIV3 (Correction when Remainder is 0).............136
Reset
Initialization of CPU Internal Register Values at Reset
............................................................33
Reset Operations.................................... ............33
Reset Priority Level............................................ 33
Restoring
Saving and Restoring Coprocessor Error Information
............................................................50
Restrictions
Data Restrictions on Word Alignment.................. 11
Program Restrictions on Word Alignment ............11
Restrictions on Interrupts during Processing of
Delayed Branching Instructions.............. 59
RET
RET (Return from Subroutine) ..........................187
RET:D (Return from Subroutine).......................201
RETI
RETI (Return from Interrupt) ............................192
Return Pointer
Overview of the Return Pointer ...........................25
Return Pointer Configuration...............................26
Return Pointer Functions.....................................26
Right Direction
ASR (Arithmetic Shift to the Right Direction)
..................................................144, 145
ASR2 (Arithmetic Shift to the Right Direction)
..........................................................146
LSR (Logical Shift to the Right Direction)
..................................................141, 142
LSR2 (Logical Shift to the Right Direction)........ 143
S
Sample
Sample Configuration of an FR Family Device....... 3
Sample Configuration of the FR Family CPU......... 4
Save
COPSV (Save 32-bit Data from Coprocessor Register
to Register)......................................... 235
Saving
Saving and Restoring Coprocessor Error Information
........................................................... 50
SCR
System Condition Code Register (SCR: Bit 10 to
bit 08).................................................. 20
Set Immediate Data
STILM (Set Immediate Data to Interrupt Level Mask
Register)................. ........................... 240
Sign Extend
EXTSB (Sign Extend from Byte Data to Word Data)
......................................................... 242
EXTSH (Sign Extend from Byte Data to Word Data)
......................................................... 244
Signed Division
DIV0S (Initial Setting Up for Signed Division)
......................................................... 128
DIV4S (Correction Answer for Signed Division)
......................................................... 137
Simultaneous Occurrences
Priority of Simultaneous Occurrences.................. 51
Software Interrupt
INT (Software Interrupt)................................... 188
INTE (Software Interrupt for Emulator) .............190
Source Register
ADD (Add Word Data of Source Register to
Destination Register)............................. 72
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register).................... 75
ADDN (Add Word Data of Source Register to
Destination Register)............................. 76
AND (And Word Data of Source Register to Data in
Memory).............................................. 86
AND (And Word Data of Source Register to
Destination Register)............................. 85
ANDB (And Byte Data of Source Register to Data in
Memory).............................................. 90
ANDH (And Half-word Data of Source Register to
Data in Memory) .................................. 88
CMP (Compare Immediate Data of Source Register
and Destination Register)....................... 83
CMP (Compare Word Data in Source Register and
Destination Register)............................. 82
EOR (Exclusive Or Word Data of Source Register to
Data in Memory) ................................ 100
EOR (Exclusive Or Word Data of Source Register to
Destination Register)............................. 99