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130nm node CMOS Process (CS90A)
Features
Technology Code |
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| CS90A |
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Transistor | UHS | HS | ST | LL |
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Physical Gate Length (nm) | 110 | 110 | 110 | 110 |
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Gate Oxide Thickness (nm) | 2.9 | 2.9 | 2.9 | 2.9 |
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Supply Voltage (V) | 1.2 | 1.2 | 1.2 | 1.2 |
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NMOS Ids (µA/µm) | 780 | 678 | 570 | 390 |
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PMOS Ids (µA/µm) |
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NMOS Ioff (nA/µm) | 36 | 4 | 0.18 | 0.005 |
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PMOS Ioff (nA/µm) |
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Mie plant | |||||||
Gate Leak Current (nA/µm) | 0.01 | 0.01 | 0.01 | 0.01 |
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Basic Gate Delay (ps) | 14 | 17 | 28 | 45 |
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Number of Available Poly Layer |
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| 1 |
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Number of Available Metal Layer |
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| 8Cu+1Al |
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Via Filling |
| Cu Dual Damascene |
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ILD Structure |
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| Hybrid |
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SRAM Cell Size (µm2) |
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| 1.98 |
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Dual Gate Oxide Options |
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| Available |
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Mixed Signal Options |
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| Available |
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RF Elements |
| MIM cap., Poly Resistor, Inductor |
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Fuse |
| RAM Redundancy |
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Technology Roadmap
| 1000 |
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| 500 | Cu |
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| Cu+Low+k |
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| Cu+VLK |
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(nm) |
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| CS80/80A |
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200 |
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Length |
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| CS90A |
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100 | CS90 |
| CS100A_LL |
| For ASIC & COT |
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Gate |
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| CS100A_G |
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50 |
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| CS200A_LL |
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Physical |
| CS100 |
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| CS200A_G |
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20 | For COT | CS200 |
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| G: Generic, LL: Low Leakage |
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| 10 |
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| 1998 | 2000 | 2002 | 2004 | 2006 | 2008 | 2010 | 2012 |
Year (Production Start)