569
APPENDIX A I/O Maps
000019HReserved
00001AHPort A direction register DDRA W Port A XXX0 0XXXB
00001BH to
00001DHReserved
00001EHPort 2 pull-up control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B
00001FHReserved
000020HSerial mode register 0 SMR0 W, R/W
UART0
0 0 0 0 0 0 0 0B
000021HSerial control register 0 SCR0 W, R/W 0 0 0 0 0 0 0 0B
000022HReception/transmission data register 0 RDR0/TDR0 R/W 0 0 0 0 0 0 0 0B
000023HSerial status register 0 SSR0 R, R/W 0 0 0 0 1 0 0 0B
000024HExtended communication control
register 0 ECCR0 R, W, R/W 0 0 0 0 0 0 XXB
000025HExtended status control register0 ESCR0 R/W 0 0 0 0 0 1 0 0B
000026HBaud rate generator register 00 BGR00 R/W, R 0 0 0 0 0 0 0 0B
000027HBaud rate generator register 01 BGR01 R/W, R 0 0 0 0 0 0 0 0B
000028HSerial mode register 1 SMR1 W, R/W
UART1
0 0 0 0 0 0 0 0B
000029HSerial control register 1 SCR1 W, R/W 0 0 0 0 0 0 0 0B
00002AHReception/transmission data register 1 RDR1/TDR1 R/W 0 0 0 0 0 0 0 0B
00002BHSerial status register 1 SSR1 R, R/W 0 0 0 0 1 0 0 0B
00002CHExtended communication control
register1 ECCR1 R, W, R/W 0 0 0 0 0 0 XXB
00002DHExtended status control register 1 ESCR1 R/W 0 0 0 0 0 1 0 0B
00002EHBaud rate generator register 10 BGR10 R/W, R 0 0 0 0 0 0 0 0B
00002FHBaud rate generator register 11 BGR11 R/W, R 0 0 0 0 0 0 0 0B
000030H to
00003AHReserved
00003BHAddress detection control register 1 PACSR1 R/W Address Match
Detection 1 0 0 0 0 0 0 0 0B
00003CH to
000047HReserved
000048HPPGC operation mode control register PPGCC W, R/W
16-bit
PPGC/D
0 X 0 0 0 XX1B
000049HPPGD operation mode control register PPGCD W, R/W 0 X 0 0 0 0 0 1B
00004AHPPGC /D count clock selection register PPGCD R/W 0 0 0 0 0 0 X 0B
Table A-1 I/O Map (2/5)
Address Register Abbreviation Access Peripheral Initial value