570
APPENDIX
00004BHReserved
00004CHPPGE operation mode control register PPGCE W, R/W
16-bit
PPGE/F
0 X 0 0 0 XX1B
00004DHPPGF operation mode control registerPPGCF W, R/W 0 X 0 0 0 0 0 1B
00004EHPPGE/F count clock selection registerPPGEF R/W 0 0 0 0 0 0 X 0B
00004FHReserved
000050HInput capture control status 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B
000051HInput capture edge 0/1 ICE01 R/W, R XXX0X0 XXB
000052HInput capture control status 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B
000053HInput capture edge 2/3 ICE23 R XXXXXXXXB
000054H to
000063HReserved
000064HTimer control status 2 TMCSR2 R/W 16-bit Reload Timer
2
0 0 0 0 0 0 0 0B
000065HTimer control status 2 TMCSR2 R/W XXXX 0 0 0 0B
000066HTimer control status 3 TMCSR3 R/W 16-bit Reload Timer
3
0 0 0 0 0 0 0 0B
000067HTimer control status 3 TMCSR3 R/W XXXX 0 0 0 0B
000068HA/D control status 0 ADCS0 R/W
A/D Converter
0 0 0 XXXX 0B
000069HA/D control status 1 ADCS1 R/W, W 0 0 0 0 0 0 0 XB
00006AHA/D data 0 ADCR0 R 0 0 0 0 0 0 0 0B
00006BHA/D data 1 ADCR1 R XXXXXX 0 0B
00006CHADC setting 0 ADSR0 R/W 0 0 0 0 0 0 0 0B
00006DHADC setting 1 ADSR1 R/W 0 0 0 0 0 0 0 0B
00006EHDetection reset control register of
low-voltage/CPU operation LVRC R /W, W Detection Reset of
Low-voltage/CPU
Operation 0 0 1 1 1 0 0 0B
00006FHROM mirror function select ROMM W ROM Mirror XXXXXXX1B
000070H to
00007FHReserved
000080H to
00008FHReserved for CAN interface. (For more information, see Table 21.3-1 .)
000090H to
00009DHReserved
00009EHAddress detection control register0 PACSR0 R/W Address Match
Detection 0 0 0 0 0 0 0 0 0B
Table A-1 I/O Map (3/5)
Address Register Abbreviation Access Peripheral Initial value