Fujitsu MB15C02 (2) The flow of serial data, Figure 4. The flow of serial data, (3) Setting the divide ratio for the programmable divider

MB15C02

(2) The flow of serial data

Serial data is received via data pin in synchronization with the clock input and loaded into shift register which contains

the divide ratio setting data and into the control register which contains the control bit. The logical product (through

the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the enable input of the

latches. Accordingly, when LE is set high, the latch for the divider identified by the control bit is enabled and the

divide ratio data from the shift register is loaded into the selected counter (s).

(3) Setting the divide ratio for the programmable divider

Columns A0 to A5 of Table 2.1 represent the divide r atio of the s w allow counter and columns N0 to N11 of Table2.2

represent the divide ratio of programmable counter.

Table. 2 Divide ratio for the programmable dividerTable.2.1 Swallow counter divider A Table2.2 Programmable counter divider N

Note: Less than 5 is prohibited.

Divide

ratio

(A) A

5Divide

ratio

(N) N

10 N

0 0 0 0 0 0 0 5 101000000000

1 1 0 0 0 0 0 6 011000000000

⋅ ⋅⋅⋅⋅⋅⋅ ⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅

63 1 1 1 1 1 1 4095 111111111111

Figure 4. The flow of serial data

14-bit binary programmable reference counter

Programmable

reference divider

14-bit latch

18-bit shift register

18-bit latch

AND

Data

Clock

Prescaler 6-bit binary swallow counter 12-bit binar y programmable

counter

Programmable

divider

* : Control register

612