Fujitsu MB15C02 (4) Setting the divide ratio for the programmable reference divider, (5) Setting data input timing, Figure 5. Serial data input timing

14
MB15C02
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of t he programma ble ref erenc e counter . The contr ol bit is set
to 1. Table.3 Divide ratio for the programmable reference divider
(5) Setting data input timing
The MB15C02 uses 19 bits of serial data for the programmable divider and 15 bits f or the progr ammab le ref erence
divider. When more bits of serial data than defined for the target divider are receiv ed , only the last valid serial data
bits are effective.
To set the divide ratio for the MB15C02 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t1 (>1 µs): Data setup time t2 (>1 µs): Data hold time t3 (> µs): Clock pulse width
t4 (>1 µs): LE setup time to the rising edge of last clock t5 (>1 µs): LE pulse width
Divide
ratio
(R) R
0R 1R 2R 3R 4R 5R 6R 7R 8R 9R 10 R 11 R 12 R 13
5 10100000000000
6 01100000000000
⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
16383 11111111111111
Data
Clock
LE
t1 t4
t5
t3
t2
Figure 5. Serial data input timing