![](/images/new-backgrounds/1294501/29450125x1.webp)
MB15E07SL
■SERIAL DATA INPUT TIMING
Data
Clock
LE
|
| 1st data | 2nd data |
|
|
| |
|
|
| Control bit Invalid data |
|
|
| ∼ |
| MSB |
| LSB |
|
|
| ∼ |
|
|
| ∼ |
t1 | t2 |
| t3 |
t7 |
|
| t6 |
|
|
| |
|
| ∼ |
|
t4
t5
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter | Min | Typ | Max | Unit |
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|
|
|
|
t1 | 20 | – | – | ns |
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t2 | 20 | – | – | ns |
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t3 | 30 | – | – | ns |
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t4 | 30 | – | – | ns |
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Parameter | Min | Typ | Max | Unit |
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|
|
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t5 | 100 | – | – | ns |
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t6 | 20 | – | – | ns |
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t7 | 100 | – | – | ns |
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Note : LE should be “L” when the data is transferred into the shift register.
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