Fujitsu MHT2020AT, MHT2030AT, MHT2040AT, MHT2060AT, MHT2080AT 4.6 Read/write Circuit

4.6 Read/write Circuit

C141-E192-01EN 4-9

4.5.3 Command processing during self-calibration

This enables the host to execute the command without waiting for a long time,

even when the disk drive is performing self-calibration. The command execution

wait time is about maximum 72 ms.

When the error rate of data reading, writing, or seeking becomes lower than the

specified value, self-calibration is performed to maintain disk drive stability.

If the disk drive receives a command execution request from the host while

performing self-calibration, it stops the self-calibration and starts to execute the

command. In other words, if a disk read or write service is necessary, the disk

drive positions the head to the track requested by the host, reads or writes data,

and then restarts calibration after 10 seconds.

If the error rate recovers to a value exceeding the specified value, self-calibration

is not performed.

4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write

circuit, the read circuit, and the time base generator in the read channel (RDC).

Figure 4.4 is a block diagram of the read/write circuit.

4.6.1 Read/write preamplifier (PreAMP)

PreAMP equips a read preamplifier and a write current switch, that sets the bias

current to the MR device and the current in writing. Each channel is connected to

each data head, and PreAMP switches channel by serial I/O. In the event of any

abnormalities, including a head short-circuit or head open circuit, the write unsafe

signal is generated so that abnormal write does not occur.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data

format, and sent to the encoder circuit in the RDC. The NRZ write data is

converted from 32-bit data to 34-bit data by the encoder circuit then sent to the

HDIC, and the data is written onto the media.

(1) 32/34 RLL MEEPRML

This device converts data using the 32/34 RLL (Run Length Limited) algorithm.

(2) Write precompensation

Write precompensation compensates, during a write process, for write non-

linearity generated at reading.

Contents

Main FOR SAFE OPERATION Page Page Preface Overview of Manual Conventions for Alert Messages Operating Environment Conventions Page Page Important Alert Items Important Alert Messages Page Manual Organization Page Contents CHAPTER 2 Device Configuration................................................................ 2-1 CHAPTER 3 Installation Conditions..............................................................3-1 CHAPTER 4 Theory of Device Operation......................................................4-1 Page Page Page Illustrations Figures Page Tables CHAPTER 1 Device Overview 1.1 Features 1.1.1 Functions and performance 1.1.2 Adaptability 1.1.3 Interface Device Overview 1-4 C141-E192-01EN 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives (MHT Serie s). Table 1.1 Specifications (1/2) 1.2.2 Model and product number 1.3 Power Requirements Page Page 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects 1.10Load/Unload Function 1.11Advanced Power Management Page Page Page 2.1 Device Configuration 2.2 System Configuration 2.2.1 ATA interface 2.2.2 1 drive connection 2.2.3 2 drives connection CHAPTER 3 Installation Conditions Page 3.2 Mounting Page Page Page Page Installation Conditions 3-8 C141-E192-01EN Figure 3.7 Handling cautions 3.3 Cable Connections 3.3.1 Device connector 3.3.2 Cable connector specifications 3.3.3 Device connection 3.4 Jumper Settings 3.4.2 Factory default setting 3.4.3 Master drive-slave drive setting 3.4.4 CSEL setting Page CHAPTER 4 Theory of Device Operation 4.1 Outline 4.2 Subassemblies 4.2.1 Disk 4.2.2 Spindle 4.2.3 Actuator 4.3 Circuit Configuration Page 4.3 Circuit Configuration DE Figure 4.2 Circuit Configurati on PCA C141-E192-01EN 4-5 4.4 Power-on Sequence 4.5 Self-calibration 4.5.1 Self-calibration contents 4.5.2 Execution timing of self-calibration 4.5.3 Command processing during self-calibration 4.6 Read/write Circuit 4.6.1 Read/write preamplifier (PreAMP) 4.6.2 Write circuit Page 4.6.3 Read circuit 4.6.4 Digital PLL circuit 4.7 Servo Control 4.7.1 Servo control circuit Page Page 4.7.2 Data-surface servo format !" # # Page 4.7.4 Actuator motor control 4.7.5 Spindle motor control Page Page CHAPTER 5 Interface 5-2 C141-E192-01EN 5.1 Physical Interface IDD 5.1.1 Interface signals Figure 5.1 shows the interface signals. Figure 5.1 Interface signals 5.1.2 Signal assignment on the connector Page Page 5.2 Logical Interface 5.2.1 I/O registers 5.2.2 Command block registers Page Page Page Page 5.2.3 Control block registers 5.3 Host Commands 5.3.1 Command code and parameters Page Page Page 5.3.2 Command descriptions Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 5.3 Host Commands C141-E192-01EN 5-107 5.3.3 Error posting 5-108 C141-E192-01EN Table 5.21 Command code and parameters (2 of 2) 5.4 Command Protocol 5.4.1 PIO Data transferring commands from device to host Page 5.4.2 PIO Data transferring commands from host to device Page 5.4.3 Commands without data transfer Page 5.4.4 Other commands 5.4.5 DMA data transfer commands Page Page 5.5 Ultra DMA Feature Set 5.5.1 Overview 5.5.2 Phases of operation 5.5.3 Ultra DMA data in commands Page Page Page Page 5.5.4 Ultra DMA data out commands Page Page Page 5.5.5 Ultra DMA CRC rules 5.5.6 Series termination required for Ultra DMA 5.6 Timing 5.6.1 PIO data transfer 5.6.2 Multiword data transfer 5-132 C141-E192-01EN 5.6.3 Ultra DMA data transfer Page Page Page Page Page Page Page Page Page Page 5.6 Timing C141-E192-01EN 5-143 Page 5.6.4 Power-on and reset Page Page 6.1 Device Response to the Reset 6.1.1 Response to power-on 6.1.2 Response to hardware reset Page 6.1.3 Response to software reset 6.1.4 Response to diagnostic command 6.2 Power Save 6.2.1 Power save mode Page 6.2.2 Power commands 6.3 Defect Processing 6.3.1 Spare area 6.3.2 Alternating processing for defective sectors Page 6.4 Read-ahead Cache 6.4.1 DATA buffer structure 6.4.2 Caching operation Page Page Page Page Page 6.5 Write Cache 6.5.1 Cache operation Page Page Page Glossary Page Page Page Acronyms and Abbreviations Page Index Page Comment Form