U4

South bridge

U5

Super I/O

 

 

U6

Clock chip

U7

64 bit Bridge

U10

LOM1

U11

LOM1 EEPROM

U12

LOM1 PHY

 

 

U13

Audio Codec

U14

Audio amplifier

U16

LOM2

U17

LOM2 EEPROM

U18

LOM2 PHY

 

 

U19

SPI ROM - SOIC-8 footprint

U20

Fan controller

U21

SPI ROM - SO16 footprint

U29

TMDS controller

U30

Parallel port diode array

U31

First serial port transceiver

 

 

U32

Second serial port transceiver

U46

VRM controller

U50

USB front port power switch

U51

First USB rear port power switch

U52

Second USB rear port power switch

 

 

U53

Third USB rear port power switch

XBT

Battery retainer

XMM1

Memory slot. DIMM1 or RIMM1 populated and tested

XMM2 - XMM5

Following memory slots

XU1

Primary processor socket

 

 

XU2

Secondary processor socket

XU15/U15

System ROM and Socket (Socket = XU15, ROM = U15)

XU19/U19

SPI ROM and socket (XU19 = socket, U19 = SPI ROM)

Y1

Primary (TH) system clock crystal

Y2

Secondary (SMT) system clock crystal

 

 

Y3

Primary NIC clock crystal

 

 

96 Appendix D System Board and Riser Board Reference Designators