4-1-6 SQUELCH CIRCUIT (RF AND MAIN UNITS)
(1) NOISE SQUELCH
The noise squelch circuit cuts out AF signals when no RF sig- nals are received. By detecting noise components in the AF signals, the squelch circuit switches the AF mute switch.
A portion of the AF signals from the FM IF IC (RF unit; IC2, pin 9) are applied to the active filter section (RF unit; IC2, pin 8). The active filter section amplifies and filters noise compo- nents. The filtered signals are applied to the noise detector section and output from pin 14 as the “SQL” signal.
The “SQL” signal from IC2 (pin 14) passes through J2 pin 9, and is then applied to the CPU (MAIN unit; IC1, pin 59). The CPU analyzes the noise condition and outputs the “RMUT” and “AFON” signals to toggle the volume mute (MAIN unit; Q23) and AF mute (MAIN unit; Q5, Q10, Q11) switches.
(2) TONE SQUELCH
The tone squelch circuit detects AF signals and opens the squelch only when receiving a signal containing a matching subaudible tone (CTCSS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open.
A portion of the AF signals from the FM IF IC (RF unit; IC2, pin 9) passes through the tone
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT (MAIN UNIT)
AF signals from the internal/external microphone are applied to the microphone amplifier circuit (IC2b) via the microphone switch (Q6). The amplified signals are passed through the
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS (RF UNIT)
The amplifier circuit amplifies the VCO oscillating signal to the output power level.
The amplified transmit signal is passed through the antenna switching circuit (D6) and
The modulated transmit signal is amplified at the
The power amplified signal is then applied to the antenna via the
4-3 PLL CIRCUITS (RF UNIT)
A PLL circuit provides stable oscillation of the transmit fre- quency and receive 1st LO frequency. The PLL output com- pares the phase of the divided VCO frequency to the refer- ence frequency. The PLL output frequency is controlled by the divided ratio
The PLL circuit consists of the VCO circuit (Q6, D4, D5). An oscillated signal from the VCO passes through the buffer amplifier (Q7) is applied to the PLL IC (IC1, pin16) and is prescaled in the PLL IC based on the divided ratio
If the oscillated signal drifts, its phase changes from that of the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency.
4-2-2 MODULATION CIRCUIT (RF UNIT)
The filtered audio signals from J4, pin 5 (On the MAIN unit) are passed through the deviation adjustment pot (R50) then applied to the modulation circuit (D4, D5) to modulate trans- mit signals at the VCO circuit (Q6).
The modulated signal is applied to the drive amplifier circuit.
• PLL circuit
VCO Buffer
Q7
D2 | to transmitter circuit |
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D1 | to 1st mixer circuit |
Loop | Q6, D4, D5 |
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filter |
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| 14 | Phase | Programmable | Prescaler | 16 |
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to the FM IF IC |
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(IC2, pin 1) | 9 |
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X1 | 11 | Programmable |
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Shift register | 7 | |||||||
DATA | ||||||||
21.25 MHz |
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