Icom IC-F21S Port Allocations, Power Supply Circuits Voltage Line, Pin Port Description Number

4-4 POWER SUPPLY CIRCUITS VOLTAGE LINE

LINE	DESCRIPTION
HV	The voltage from the attached battery pack.
	The same voltage as the HV line (battery volt-
VCC	age) which is controlled by the power swtich
	([VOL] control).
	Common 5 V converted from the VCC line by the
CPU5V	+5 regulator circuit (IC10). The output voltage is
	applied to the CPU (IC7), reset circuit (IC8) and
	etc.
T5V	5 V for transmitter circuits regulated by the T5
	regulator circuit (Q27).
R5V	5 V for receiver circuits regulated by the R5 reg-
	ulator circuit (Q26).
S5V	Common 5 V converted from the VCC line by the
	S5 regulator circuit (Q24, Q19).
+5V	The same voltage as the CPU5V line for the ana-
	log swtich (IC6), buffer amplifier (Q13), etc.
	The same voltage as the +5V line for the TX-
VCO5V	VCO (Q11), RX-VCO (Q10) and buffer amplifiers
	(Q5–Q7).

4-5 PORT ALLOCATIONS

4-5-1 CPU (IC7)

Pin	Port	Description
number	name
7	RES	Input port for RESET signal.
13	SENC0
14	SENC1	Outputs single tone encode signal.
19	SENC2
20	SENC3
23	CENC0
24	CENC1	Outputs CTCSS/DTCS data signal.
25	CENC2
28	SCK	Outputs serial clock signal to the PLL
		IC (IC1), EEPROM (IC11), etc.
29	SO	Outputs data signal to the PLL IC
		(IC1) and D/A convertor (IC9).
30	BEEP	Outputs beep audio signal.
36	PLST	I/O port for strobe signal from/to PLL
		IC (IC9).
		• Outputs strobe signal to the D/A con-
37	DAST	vertor (IC9).
		• Input port for the initial version sig-
		nal.
38	EXST	Outputs strobe signal for the expander
		IC (IC15).
39	PTT	Input port for [PTT] swtich signal.
		High: While [PTT] switch is pushed.
40	TXC	Outputs TX mute control signal.
		High: While transmitting
41	RLED	Outputs BUSY LED control signal.
		High: While receiving.
42	TLED	Outputs TX LED control signal.
		high: While transmitting.
		Outputs control signal for the regulator
43	AFON	circuit of AF power amplifier.
		High: While squelch is open, etc.
44	ESDA	I/O port for data signal from/to the
		EEPROM (IC11).
45	CLI	Input port for cloning signal.
46	CLO	Outputs the cloning signal.
51	F1	Input ports for the customization key
52	F2	signals.
53	NOIS	Input port for the noise pulse signal for
		the squelch function.
54	UNLK	Input port for PLL unlock signal.
		High: PLL is locked.
55	TEMP	Input port for the transceiver’s internal
		tempereture detection.
57	CDEC	Input port for CTCSS/DTCS signals.
58	SDEC	Input port for single tone decode sig-
		nal.
59	RSSI	Input port for the RSSI voltage.
60	LVIN	Input port for the PLL lock voltage.

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