SECTION 3 CIRCUIT DESCRIPTION
Received signals from the antenna connector are applied to the transmit/receive switching and protection relay (FILTER unit; RL7301) which is controlled by the CPU via the “TRXS” line. The signals pass through the 30 MHz
The signals pass through the transmit/receive switch (D53) and 1.6 MHz cut off
The filtered signals pass through the 33 MHz
Frequency (MHz) | LPF ctrl signal | BPF ctrl signal |
L0 | B0 | |
L1 | B1 | |
L2 | B2 | |
L3 | B3 | |
L4 | B4 | |
L5 | B5 | |
L6 | B6 | |
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L7 |
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The 1st mixer circuit converts the received signals into a fixed frequency, 64.445 kHz 1st IF signal using PLL output frequency. By changing the PLL frequency, only the desired frequency is picked up at the pair of crystal filters (FI301a, FI301b) via the 64.445 kHz bandpass filter (FI201) at the next stage.
The IF amplifier (Q203) and resonator circuits are designed between the filter pair. The PLL output signal (1LO) enters the MAIN unit via the J601 and is amplified at the 1st LO amplifier (Q601). The amplified signal is passed through the
100MHz
The 1st IF signal from the crystal filter (FI301b) is converted again into a 455 kHz 2nd IF signal at the 2nd mixer circuit (D302, L303, L304). The 2nd LO signal (2LO) from the PLL unit enters the MAIN unit via the J301 to be applied to the 2nd mixer circuit.
The 2nd IF signal passes through the
The DSP (Digital Signal Processor) circuit enables digital IF filter, digital noise reduction, digital PSN (Pulse Shift Network), phase demodulation, digital automatic notich, and etc.
The 3rd IF signal is applied to the IF amplifier (MAIN unit; IC1002, pin 5) after being passed through the
•RECEIVER CONSTRUCTION
Antenna
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| 1st LO |
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LPF |
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| LPF |
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| Crystal |
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FILTER unit |
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| FI301A | FI401 | Q401 | |||||||
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| Q201 | Q201 | |||||||||
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| BPF |
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| FI301B |
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| Q202 |
| Q202 |
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3rd LO
443 kHz
to transmit/receiver switch
IF | LPF | IF | Crystal |
amp. | amp. | BPF | |
IC1002 |
| 3rd mixer Q501 | FI402 |
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| IC501 |
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