Intel 80302, 80303 specifications

Intel® 80303 and 80302 I/O

Processors

Specification Update

May 6, 2003

Notice: The Intel® 80303 and Intel® 80302 I/O Processors process or may cont ain desi gn defect s

or errors known as errata. Characterized errat a that may cause the product’s behavior to deviate

from pubished specifications are documented in this specification update.

Order Number: 273355-010

Contents

Main Intel 80303 and 80302 I/O Processors Specification Update Contents Page Revision History Revision History Preface Affected Documents/Related Documents Nomenclature Summary Table of Changes Codes Used in Summary Table Stepping Page Status Errata Specification Changes Specification Clarifications Summary Table of Changes Documentation Changes Identification Information Identification Information Intel 80303 I/O Processor Markings Topside Markings Die Details Device ID Registers Errata 1. Single-bit and Multi-bit Error Reporting Cannot Be Individually Enabled by ECC Control Register 2. Instruction Sequence Can Scoreboard a Register Indefinitely Page Specification Changes 1. Summary of the Intel 80302 I/O Proce ssor Specification Clarifications 1. ECC is Always Enabled 2. 32-bit SDRAM is Not Supported 3. Non-Battery Backup Systems 4. POCCDR and SOCCDR Functionality 6. SREQ64# Functionality 7. PCI Local Bus Specification , Revision 2.3 Compliancy 8. DMA and AAU End of Chain Functionality Intel 80303 and 80302 I/O Processors Specification Update 17 Documentation Changes 1. Title Page revision number Number 272353-001. The extension -001 is the correct revision number for this document. 2. Figure 9-3 on pg 9-9 did not print correctly Fault Data 3. Figure 13-22 on pg 13-40 did not print correctly 4. Figure 13-18, pg 13-35 Intel 80303 and 80302 I/O Processors Specification Update 19 5. Figure 15-2 on pg 15-3 did not print correctly Affected Docs: Intel 80303 I/O Processor Dev elopers Manual. Secondary PCIPrimary PCI Secondary ATU PCI Master/Slave IB Master/Slave Intel 80303 and 80302 I/O Processors Specification Update 21 8. Table 24-4 on pg 24-8 is incorrect Table 24-4. Intel Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 2 of 10) Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sh eet 3 of 10) Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 4 of 10) Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sh eet 5 of 10) Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 6 of 10) Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sh eet 7 of 10) Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 8 of 10) Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sh eet 9 of 10) 30 Intel 80303 and 80302 I/O Processors Specification Update Affected Docs: Intel 80303 I/O Processor Developers Manual. Table 24-4. Intel 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 10 of 10) Intel 80303 and 80302 I/O Processors Specification Update 31 9. Figure 25-1 on pg 25-1 has incorrect data Clock Region 4 Clock Region 1 10. Section 25.1.3 on page 25-2 is 66MHz. It is actually 100 MHz. 11. Figure 25-2 on pg 25-2 did not print correctly 12. Table 25-2 on page 25-3 did not print completely 13. Section 1.2.2 on page 1-2 has incorrect data 14. Figure 12-2 on page 12-10 has incorrect data 15. Section 19.1 on page 19-1 has incorrect data 16. Table 14-46 on page 14-109 has mi ss ing data 17. Section 13.2.4.3 o n page 13 -30 has incorrect data 18. Figure 15-3 on page 15-7 has missing text 19. Section 15.7.39 on page 1 5-100 has incorrect data Intel 80303 and 80302 I/O Processors Specification Update 35 20. Table 8-17 on page 8-38 has incor r ec t data 21. Section 11.2.8 on page 11-5 has incorrect data Workaround: Change text to the following: 'The 80303 I/O processor complies with the PCI Local Bus Specification, Revision 2.2. Reset parameters are defined in this specification.' 22. Section 13.2.3.1 on page 13-13 has incorrect data 24. Table 8-15 on page 8-36 needs clar ification 25. Table 13-13 on page 13-30 has incorrect data 26. Section 13.2.4.3, F i rs t Pa ragraph after Table 13-13 has Incorr ec t Data 27. Section 13.2.4.3, First Paragraph after Current Figure 13-16. H-Matrix has Incorrect Data 28. Section 11.3.1.5 FAIL# Code 29. Section 13.5 Reset Conditions has Incorrect Data 30. Section 13.2.4.2, First Sentence has Incorrect Data 32. Section 4.5.2 on page 50 is only correct for A-0 and A-1 steppings 33. Section 17.5.1 on page 17-12 is only correct for A-0 and A-1 steppings