Intel 80302, 80303 Errata

Errata

12 Intel® 80303 and 80302 I/O Processors Specification Update

Errata

Problem: The ECC Control Register ECCR is described as having the ability to select multi-bit error and/or

single-bit error reporting (see Table 13-24 on page 13-31 of the Intel® 80303 I/O Processor

Developer’s Manual). However, the algorithm does not allow individual enabling; that is, the

reporting is either on or off for both multi-bit and single bit error reporting.

Implication: The error reporting selection (enabled or di sabled) will apply t o bot h mult i-bit a nd sin gle-bit er rors.

Workaround: There is no current workaround. If either the ECCR.0 bit or the ECCR.1 bit is selected for

reporting, then both multi-bit and single-bit error report ing are enable d. If neither bit is selecte d for

reporting, then both multi-bit and single-bit error reporting are disabled.

Status: NoFix. See the Table “Summary Table of Changes” on page7.

Problem: Register scoreboarding maintains register coherency by preventing parallel execution units from

accessing registers for which there is an outstanding operation (see section 3.2.3 in the Intel®

80303 I/O Processor Developer’s Manual).

An instruction sequence that coincides with some specific instruction cache conditions can

scoreboard a local or global register indefinitely. When this happens, processing can stall at the

next access to tha t register, awaiting a s coreboard release that does not com e. In that case, e xternal

bus accesses cease.

A hardware reset is the only way to release the scoreboard.

The following three conditions are required to scoreboa rd a register:

1. Execution of the following three-instruction seque nce:

a. emul

b. ld, ldos, ldis, ldob, or ldib

c. mulo or muli

Only two-word, MEMB format load instructions that execute in tw o cl oc k cycles cause the

failure. Ta ble 1 lists all the versions of these instructions that can produce this failure. Any

version can be used for each instruction and still produce the failure as long as the sequential

order is maintained.

2. The emul must appear at address 0xXXXXXXX8.

3. Instruction caching must be enabled. The emul instruction must be fetch ed from external

memory along with the first word of the load instruction. Also, the second word of the load

and the multiply instruction must already reside in cache. To accomplish this, th e code must

have run once in order to load the instructions into cache followed by code which causes the

invalidation of the cache line containing the emul instruction. At this point, re-execution of the

code sets up the failure condition.

Once the failure condition occurs, the processor will continue code execution until an instruction

using the scoreboarded register is encountered, then indefinite processor stall will occur.