1.4.19LED 1 Configuration and Power Management (Word 17h)
This field specifies the default values for the LEDCTL register fields controlling the LED1 (LINK_1000) output behaviors and the OEM fields defining the PHY power management parameters loaded to the PHY_CTRL register.
Table 15. | LED 1 Configuration and Power Management (Word 17h) | ||||
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| Bit | Name | Default |
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| This bit enables Smart Power Down in | |
| 15 | B2B Enable | 1b | 0b = B2B disabled. | |
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| 1b | = B2B enabled. |
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| GbE Disable (in all power states) | |
| 14 | GbE Disable | 0b | 0b = GbE enabled. | |
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| 1b | = GbE disabled. |
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| 13:12 | Reserved | 00b | These bits are reserved and should be set to 00b. | |
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| GbE Disable in non- |
| GbE Disable (in all power states except D0a) | |
| 11 | 1b | 0b | = GbE enabled. | |
| D0a | ||||
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| 1b | = GbE disabled. | |
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| The Low Power Link Up enables link at the lowest speed supported | |
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| LPLU Enable in non- |
| by both link partners in | |
| 10 | 1b | LPLU Enable bit is set. | ||
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| 0b | = Low Power Link Up is disabled. |
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| 1b | = Low Power Link Up is enabled in all |
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| The Low Power Link Up enables link at the lowest speed supported | |
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| by both link partners in all power states. This bit enables a | |
| 9 | LPLU Enable | 0b | decrease in link speed in all power states. | |
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| 0b | = Low Power Link Up is disabled. |
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| 1b | = Low Power Link Up is enabled in all power states. |
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| 8 | SPD Enable | 1b | 0b | = PHY Smart Power Down mode is disabled. |
| 1b | = PHY Smart Power Down mode is enabled. | |||
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| This bit indicates the initial value of the LED1_BLINK field. | |
| 7 | LED1 Blink | 0b | 0b = LED1 is | |
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| 1b | = LED1 is blinking. |
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| This bit indicates the initial value of the LED1_IVRT field. | |
| 6 | LED1 Invert | 0b | 0b = LED1 has an active low output. | |
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| 1b | = LED1 has an active high output. |
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| This bit defines the LED1 blink mode: | |
| 5 | LED1 Blink Mode | 0b | 0b | = Blink at 200 ms on and 200 ms off. |
| 1b | = Blink at 83 ms on and 83 ms off. | |||
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| This field should be identical to LED0 Blink Mode. | |
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| Enable Filtered Activity LED (while operating with the 82562V) | |
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| When set to 0b, the activity LED is activated by the PHY. | |
| 4 | Filtered ACT LED | 0b | When set to 1b, the activity LED is driven by Tx activity or Rx | |
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| traffic that match any of the MAC's MAC addresses. | |
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| For the 82566, this bit is reserved and should be set to 0b. | |
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| These bits represent the initial value of the LED1_MODE field, | |
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| which specifies the event, state, or pattern displayed on LED1 | |
| 3:0 | LED1 Mode | 0111b | (LINK_1000) output. Table 16 defines the values for LED1 Mode. | |
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| A value of 0111b indicates that a 1000 Mb/s link is established and | |
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| maintained. | |
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The following table lists the LED modes defined in bits 3:0 of this word.
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