Intel IB935 user manual Advanced Chipset Features, DRAM Timing Selectable, CAS Latency Time

BIOS SETUP

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.

Phoenix - AwardBIOS CMOS Setup Utility

Advanced Chipset Features

DRAM Timing Selectable	By SPD	ITEM HELP
CAS Latency Time	Auto	Menu Level >
DRAM RAS# to CAS# Delay	Auto
DRAM RAS# Precharge	Auto
Precharge dealy (tRAS)	Auto
System Memory Frequency	By SPD
System BIOS Cacheable	Enabled
Memory Hole at 15M-16M	Disabled
PCI Express Root Port Func	Press Enter
** VGA Setting **
PEG/On Chip VGA Control	Auto
On-Chip Frame Buffer Size	8MB
DVMT Mode	DVMT
DVMT/FIXED memory Size	128MB
SDVO Device Setting	None
SDVO LVDS Protocol	1 Ch 18bit
SDVO Panel Number	852 x 480
Boot Display	Auto
Panel Scaling	Auto
Panel Number	1024 x 768 18bit SC
Onboard Lan Boot ROM	Enabled
Onboard IT8211F IDE ROM	Enabled

DRAM Timing Selectable

This option refers to the method by which the DRAM timing is selected. The default is By SPD.

CAS Latency Time

You can select CAS latency time in HCLKs of 3/3 or 4/4. The system board designer should set the values in this field, depending on the DRAM installed. Do not change the values in this field unless you change specifications of the installed DRAM or the installed CPU. The choices are 3, 4 and 5.

DRAM RAS# to CAS# Delay

This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS (Column Address Strobe) signals. This delay occurs when the SDRAM is written to, read from or refreshed. Reducing the delay improves the performance of the SDRAM.

DRAM RAS# Precharge

This option sets the number of cycles required for the RAS to accumulate its charge before the SDRAM refreshes.

32 IB935 User’s Manual