Intel IQ31244 user manual 3.2General-PurposeI/O Unit, 3.3I2C Bus Units, GPIO Signal Definitions

Intel® IQ31244 Customer Reference Board

3.2General-Purpose I/O Unit

The Intel® 80321 I/O Processor has eight general-purpose I/O GPIO[7:0] pins to control or monitor external devices in the I/O subsystem:

•The GPIO[0] and GPIO[1] signals are for CompactFlash* status.

•The GPIO[2] signal can be set to sound the buzzer. The buzzer can be disabled by adding a jumper onto Z14.

•The Flash ROM signal VPEN is assigned to GPIO[4] to allow software connection for code/data protection.

•The Flash ROM signal STS is assigned to GPIO[5] to allow interrupt input from the Flash ROM.

•The GPIO[6] and GPIO[7] signals are for the I2C bus.

Table 9. GPIO Signal Definitions

GPIO		Signal
7	Port 0	SCL
6	Port 0	SDA
5	Port 1	SCL/Flash_VPEN
4	Port 1	SDA/Flash_STS
3	Watchdog Timer
2	Buzzer
1	Compact Flash Wait
0	Compact Flash Ready/Busy

3.3I2C Bus Units

The IQ31244 has two Inter-Integrated Circuit (I2C) bus units. The first I2C bus interfaces the Intel® 80321 I/O Processor with the other I2C peripherals and microcontrollers for system management functions. Both buses allow the processor to serve as a master and slave device residing on the I2C bus. The first I2C has four components attached to the processor: the SDRAM EEPROM, the two temperature sensors, and the reset supervisor (with I2C addresses as shown in Table 10). The second I2C bus interface is through J15, a 4-pin header with pin 1 as SDA and pin 2 as SCL.

Table 10.	I2C Device Addresses
	Designator	Device	Function	Address
	J8	DDR SDRAM	Memory configuration	1010	0000
		EEPROM DIMM
	U35	LM75	Temperature sensor	1001 000x
	U8	LM75	Temperature sensor	1001 001x
	U7	ST-M41ST85W	Reset supervisor	1101	000x

User’s Manual 19