Schematic Diagrams

B - 12 DDRII SO-DIMM 1/2

B.Schematic Diagrams
DDRII SO-DIMM 1/2
Sheet 11 of 43
DDRII SO-DIMM 1/2
VTT_MEM12,34
R323 39_04
1.8V
MEM_0_DATA 5 9
MEM_0A_ADD2
C418 0.1u_X7R_04
MEM_0_DQS#[0..7]8
MEM_0_DQM0
MEM_0A_ADD0
MEM_0_DATA 0
MEM_0A_ADD6
1.8V
MEM_0_DATA 3 6
C397 0.1u_X7R_04
C422
0.1u_X7R_04
MEM_0_DATA 4 6
MEM_0_DQM4
MEM_0_DATA 3 0
MEM_0_DQS6
MEM_0A_ADD7
MEM_0A_ADD0
MEM_0A_WE#8
MEM_0_DATA 5 1
MEM_0_DATA 5 7
JDIMM-2A
AS0A421-NASN-4F
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
107
106
108
109
113
110
115
79
80
30
32
164
166
195
197
200
198
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
114
119
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
BA0
BA1
RAS#
WE#
CAS#
S0#
S1#
CKE0
CKE1
CK0
CK0#
CK1
CK1#
SDA
SCL
SA1
SA0
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
ODT0
ODT1
C415 0.1u_X7R_04
MEM_0A_CS#08
MEM_0_DATA 5 5
MEM_0A_CLK0#8
MEM_0_DQS#7
MEM_0A_ADD1
MEM_0_DQS#[0..7]
MEM_0A_CS#0
Layout Note:
VTT_MEM
MEM_0A_ODT08
MEM_0A_CLK18
MEM_0_DQS4
C416 0.1u_X7R_04
C402
0.1u_X7R_04
ICH_SMBCLK2,12,17,19,26
MEM_0A_CAS#8
MEM_0A_BA18
MEM_0_DATA 3 9
MEM_0A_CS#0
R314 1K_1%_04
MEM_0_DATA 1 6
MEM_0_DATA 1 8
MEM_0_DATA 6 1
MEM_0_DATA 2 3
MEM_0A_BA1
R322 39_04
MEM_0A_ADD2
C388
10u_10V_08
MEM_0_DATA 1 9
MEM_0A_ADD4
C395 0.1u_X7R_04
C398 0.1u_X7R_04
MEM_0_DATA 3 7
MEM_0_DATA 9
JDIMM-2B
AS0A421-NASN-4F
112
111
117
96
95
118
81
82
87
103
88
104
199
83
120
50
69
163
1
201
202
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
NC1
NC2
NC3
NC4
NCTEST
VREF
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
R311
1K_1%_04
MEM_0A_ADD4
MEM_0_DATA 4 8
signal/space/signal:
MEM_0A_ODT18
MEM_0A_CKE1
C392
10u_10V_08
MEM_0_DATA 5
MEM_0_DATA 2
CLOSE TO SO-DIMM_0
VTT_MEM
MEM_0_DATA 5 2
MEM_0_DATA 2 6
MEM_0_DATA 2 8
MEM_0_DQM[0..7]
MEM_0_DATA 4 2
MEM_0A_RAS#
MEM_0A_ADD3
MEM_0A_CAS#
MEM_0A_ADD14
MEM_0A_CLK1
MEM_0A_ODT1
MEM_0A_BA08
MEM_0_DQM6
MEM_0_DATA 6 3
MEM_0A_BA1
MEM_0A_WE#
MEM_0_DATA 2 1
RN27 33_04_8P4R
1
2
3
4 5
6
7
8
MEM_0_DATA 3 3
MEM_0A_ADD5
MEM_0_DATA 5 4
MEM_0_DQS5
MEM_0_DATA[0..63]8
MEM_0A_BA28
MEM_0_DATA 5 0
MEM_0A_ADD5
C394 0.1u_X7R_04
C5
0.1u_X7R_04
MEM_0A_ADD1
MEM_0A_ADD8
C410
0.1u_X7R_04
MEM_0_DQS7
MEM_0A_ODT1
MEM_0_DQM[0..7]8
MEM_0_DATA 5 6
MEM_0_DQS2
MEM_0A_ADD9
+
C431
100u_10V_D
1.8V 7, 8, 10 ,1 2, 31, 34
MEM_0A_CLK08
MEM_0_DATA 1 4
MEM_0_DATA 6
MEM_0A_BA0
MEM_0_DATA 5 8
MEM_0_DATA 3 8
C419 0.1u_X7R_04
MEM_0_DATA 4 0
MEM_0_DQS[0..7]
MEM_0_DATA 1 7
MEM_0_DQS#4
MEM_0A_CLK1#
MEM_0_DATA 8
MEM_0A_ADD14
MEM_0_DQS0
C389
10u_10V_08
C399 0.1u_X7R_04
MEM_0_DATA 1 2
MEM_0_DATA 7
MVREF_DIM0
MEM_0A_CAS# R316 39_04
RN30 33_04_8P4R
1
2
3
4 5
6
7
8
MEM_0A_CS#18
MEM_0_DATA 4 3
MEM_0A_CKE0
MEM_0A_RAS#
MEM_0_DQM3
MEM_0A_CS#1
9 / 5 / 9
MEM_0_DATA 4 4
C412
1u_10V_06
MEM_0_DATA 6 2
R317 39_04
MEM_0_DATA 4 7
MEM_0A_BA2
MEM_0_DQS#2
MEM_0A_ODT0
MEM_0_DATA 2 9
MEM_0A_ADD11
MEM_0_DQS#6
MEM_0_DATA 3 2
3.3VS
MEM_0_DATA 2 2
MEM_0_DATA 3
MEM_0A_CLK0
C384
0.1u_X7R_04
MEM_0A_BA2
MEM_0A_CLK0#
C414 0.1u_X7R_04
C413 0.1u_X7R_04
MEM_0A_WE#
MEM_0A_BA0
C401
0.1u_X7R_04
MEM_0_DATA 1 3
MVREF_DIM0
RN29 33_04_8P4R
1
2
3
4 5
6
7
8
R320 39_04
C393 0.1u_X7R_04
MEM_0_DATA 4 9
RN28 33_04_8P4R
1
2
3
4 5
6
7
8
3.3VS2,7,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,28,29,30,31,37
ICH_SMBDAT2,12,17,19,26
MEM_0_DATA 4 5
MEM_0_DATA 1 5
MEM_0A_ADD13
MEM_0A_ODT0
C404
0.1u_X7R_04
MEM_0_DATA 3 4
C436
10u_10V_08

SO-DIMM 0

C386
0.1u_X7R_04
MEM_0_DQS1
MEM_0A_ADD10
MEM_0A_ADD7
MEM_0A_CKE08
MEM_0_DATA 4 1
MEM_0_DQM1
MEM_0A_ADD8
MEM_0_DATA 6 0
MEM_0_DATA 2 5
MEM_0A_ADD12
MEM_0_DATA 5 3
16-56034-45A
MEM_0A_ADD9
+
C485
*220u/4V_V
MEM_0A_ADD13
C396 0.1u_X7R_04
MEM_0_DATA 3 5
MEM_0_DATA 1 0
MEM_0_DQS3
+
C785
100u_10V_D
C387
10u_10V_08
R324 33_04
MEM_0_DATA 1
MEM_0A_ADD11
MEM_0_DQM7
MEM_0A_CKE0
MEM_0A_ADD10
C6
0.1u_X7R_04
MEM_0_DATA 1 1
MEM_0A_CKE1
R315 39_04
C408
0.1u_X7R_04
MEM_0A_CLK1#8
MEM_0_DQS#3
MEM_0A_ADD12
1.8V
MEM_0_DQS#5
MEM_0_DQS#1
MEM_0_DQS[0..7]8
MEM_0_DQS#0
MEM_0A_CS#1
C7
0.1u_X7R_04
Layout note:
MEM_0A_ADD[0..14]8
MEM_0_DATA 2 0
RN26 33_04_8P4R
1
2
3
4 5
6
7
8
MEM_0_DATA 2 4
MEM_0A_ADD3
MEM_0_DQM2
C417 0.1u_X7R_04
MEM_0_DATA 3 1
MEM_0A_ADD6
C433
10u_10V_08
R321 33_04
VTT_MEM RESISTORS
MEM_0A_RAS#8
MEM_0_DQM5
MEM_0_DATA 4
MEM_0_DATA 2 7
MEM_0A_CKE18
Place one cap close to every 2 pull-up resistorsterminated to +VTT_MEM