Intel SSDSA2BW120A301, SSDSC2CW060A3K5, SSDSC2CW120A310, SSDSC2CW240A310, SSDSC2CW480A301, SSDSC2CW480A310 4.0 Pin and Signal Descriptions

Intel® Solid-State Drive 520 Series

February 2012 Product Specification

Order Number: 325968-001US 13

Intel® Solid-State Drive 520 Series

4.0 Pin and Signal Descriptions

4.1 Pin Locations

Note: 2.5-inch connector supports in-built latching capability.

4.2 Signal Descriptions

4.2.1 Connector Pin Signal Definitions

Note: Key and spacing separate signal and power segments.

Figure 3. Layout of Signal and Power Segment Pins

Table 9. Serial ATA C onnector Pin Signal Definitions

Pin Function Definition

S1 Ground 1st mate

S2 A+ Differential signal pair A

S3 A-

S4 Ground 1st mate

S5 B- Differential signal pair B

S6 B+

S7 Ground 1st mate

Signal Segment S1 Power Segment P1

Contents

Main Intel Solid-State Drive 520 Series Product Specification Intel Solid-State Drive 520 Series Product Specification February 2012 2Order Number: 325968-001US Ordering Information Contact your local Intel sales representative for ordering information. Contents Page 1.0 Overview 2.0 Product Specifications 2.1 Capacity 2.2 Performance Table 1. User Addressable Sectors Table 2. Compressible Performance Table 3. Incompressible Performance Table 4. Latency 2.3 Electrical Characteristics 2.4 Environmental Conditions Table 5. Operating Voltage and Power Consumption Table 6. Temperature, Shock, Vibration 2.5 Product Regulatory Compliance 2.6 Reliability 2.7 Hot Plug Support 3.0 Mechanical Information Page 4.0 Pin and Signal Descriptions 4.1 Pin Locations Signal Segment S1 Power Segment P1 4.2 Signal Descriptions 4.2.1 Connector Pin Signal Definitions 4.2.2 Power Pin Signal Definitions Table 10. Serial ATA Power Pin Definitions 5.0 Supported Command Sets 5.1 ATA General Feature Command Set 5.2 Power Management 5.3 Security Mode Feature Set 5.4 SMART Command Set 5.4.1 SMART At tribut es Table 11. SMART Attributes (Continued) 5.4.2 SMART Logs 5.5 Device Statistics 5.6 SMART Command Transport (SCT) 5.7 Data Set Management Command Set 5.8 Host Protected Area Command Set 5.9 48-Bit Address Command Set 5.10 General Purpose Log Command Set 5.11 Native Command Queuing 5.12 Software Settings Preservation 5.13 SATA Link Power Management (LPM) 6.0 Certifications and Declarations 7.0 References Tab le 15 identifies the standards information referenced in this document. Tab le 16 defines the terms and acronyms used in this document. 8.0 Terms and Acronyms Table 15. Standards References 9.0 Revision History Table 16. Glossary of Terms and Acronyms (Continued) Appendix A IDENTIFY DEVICE Command Data Page Table 17. Returned Sector Data (Continued)

Intel 4.0 Pin and Signal Descriptions

Models: SSDSA2BW120A301 SSDSC2CW060A3K5 SSDSC2CW120A310 SSDSC2CW240A310 SSDSC2CW480A301 SSDSC2CW480A310