Intel SSDSA2BW120A301, SSDSC2CW060A3K5, SSDSC2CW120A310, SSDSC2CW240A310, SSDSC2CW480A301, SSDSC2CW480A310 4.2.2 Power Pin Signal Definitions

Intel® Solid-State Drive 520 Series

Intel® Solid-State Drive 520 Series

Product Specification February 2012

14 Order Number: 325968-001US

Intel® Solid-State Drive 520 Series

4.2.2 Power Pin Signal Definitions

Notes:

1. All pins are in a single row, with a 1.27 mm (0.050-inch) pitch.

2. Pins P1, P2 and P3 are connected together; Pins P13, P14 and P15 are connected together. Although they are not

connected internally to the device, the host may apply voltage on these pins.

3. The mating sequence is:

• Ground pins P4-P6, P10, P12 and the 5V power pin P7.

• Signal pins and the rest of the 5V power pins P8-P9.

4. Ground connectors P4 and P12 may contact before the other 1st mate pins in both the power and signal connectors to

discharge ESD in a suitably configured backplane connector.

5. Power pins P7, P8, and P9 are internally connected to one another within the device.

6. The host may ground P11 if it is not used for Device Activity Signal (DAS).

Table 10. Serial ATA Power Pin Definitions

Pin1Name Definition Mating Order

P12V33 3.3 V Power; not used 2nd Mate

P22V33 3.3 V Power; not used 2nd Mate

P32V33 3.3 V Power; not used 1st Mate

P43,4 Ground 1st Mate

P53Ground 1st Mate

P63Ground 1st Mate

P73,5 V55 V Power 1st Mate

P83,5 V55 V Power 2nd Mate

P93,5 V55 V Power 2nd Mate

P103Ground 1st Mate

P116DAS Device Activity Signal 2nd Mate

P123, 4 Ground 1st Mate

P132V12 12 V Power; not used 1st Mate

P142V12 12 V Power; not used 2nd Mate

P152V12 12 V Power; not used 2nd Mate

Contents

Main Intel Solid-State Drive 520 Series Product Specification Intel Solid-State Drive 520 Series Product Specification February 2012 2Order Number: 325968-001US Ordering Information Contact your local Intel sales representative for ordering information. Contents Page 1.0 Overview 2.0 Product Specifications 2.1 Capacity 2.2 Performance Table 1. User Addressable Sectors Table 2. Compressible Performance Table 3. Incompressible Performance Table 4. Latency 2.3 Electrical Characteristics 2.4 Environmental Conditions Table 5. Operating Voltage and Power Consumption Table 6. Temperature, Shock, Vibration 2.5 Product Regulatory Compliance 2.6 Reliability 2.7 Hot Plug Support 3.0 Mechanical Information Page 4.0 Pin and Signal Descriptions 4.1 Pin Locations Signal Segment S1 Power Segment P1 4.2 Signal Descriptions 4.2.1 Connector Pin Signal Definitions 4.2.2 Power Pin Signal Definitions Table 10. Serial ATA Power Pin Definitions 5.0 Supported Command Sets 5.1 ATA General Feature Command Set 5.2 Power Management 5.3 Security Mode Feature Set 5.4 SMART Command Set 5.4.1 SMART At tribut es Table 11. SMART Attributes (Continued) 5.4.2 SMART Logs 5.5 Device Statistics 5.6 SMART Command Transport (SCT) 5.7 Data Set Management Command Set 5.8 Host Protected Area Command Set 5.9 48-Bit Address Command Set 5.10 General Purpose Log Command Set 5.11 Native Command Queuing 5.12 Software Settings Preservation 5.13 SATA Link Power Management (LPM) 6.0 Certifications and Declarations 7.0 References Tab le 15 identifies the standards information referenced in this document. Tab le 16 defines the terms and acronyms used in this document. 8.0 Terms and Acronyms Table 15. Standards References 9.0 Revision History Table 16. Glossary of Terms and Acronyms (Continued) Appendix A IDENTIFY DEVICE Command Data Page Table 17. Returned Sector Data (Continued)