JVC KD-LX555R service manual 4.16TC94A14FA IC1621 DSP & DAC

4.16TC94A14FA (IC1621) : DSP & DAC

• Terminal layout & block daiagram

48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33
49															32
50		Clock													31
		generator						PWM					D/A
51															30
LPF
52			1-bit						Servo				A/D		29
			DAC
53									control
															28
54															27
55					Address				ROM	Digital equalizer					26
						circuit				automatic
56									RAM	adjustment circuit					25
57				Correction circuit		RAM									23
													Data		24
									CLV servo
58						16 k							slicer
59								Synchronous							22
									guarantee
60									EFM				VCO		21
									decoder
61			Audio out			Digital									20
			circuit			output
		Micro-
62
	controller								Sub code				PLL		19
	interface
63									decoder				TMAX		18
64															17
1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16

• Pin function

Pin	Symbol	I/O	Descroption
No
1	BCK	O	Bit clock output pin.32fs48fsor 64fs selectable by command.
2	LRCK	O	L/R channel clock output pin."L" for L channel and "H" for R channel.
			Output polarity can be inverted by command.
3	AOUT	O	Audio data output pin. MSB-first or LSB-first selectable by command.
4	DOUT	O	Digital data output pin.Outputs up to double-speed playback.
5	IPF	O	Correction flag output pin. When set to "H" AOUT output cannot be corrected by C2 correction processing.
6	VDD3	-	Digital 3.3V power supply voltage pin.
7	VSS3	-	Digital GND pin.
8	SBOK	O	Subcode Q data CRCC result output pin. "H" level when result is OK.
9	CLCK	O	Subcode P-W data read I/O pin. I/O polarity selectable by command.
10	DATA	O	Subcode P-W data output pin.
11	SFSY	O	Playback frame sync signal output pin.
12	SBSY	O	Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected.
13	HSO	I/O	General-purpose input / output pins.Input port at reset.
14	UHSO
15	PVDD3	-	PLL-only 3.3V power supply voltage pin.
16	PDO	O	EFM and PLCK phase difference signal output pin.

1-48 (No.49793)