LG Electronics 32LA62**-Z* Copyright 2013 LG Electronics. Inc. All rights reserved, DDR512MBSS

DDR_512MB_SS

DDR_512MB_SS

+1.5V_DDR
A_RVREF1	C713
R706	0.1uF
1K
1%
R707	C714
1K
1%	0.1uF
+1.5V_DDR
A_RVREF4	C715
R708	0.1uF
1K
1%
R709	C716
1K
1%	0.1uF

				IC701
			K4B4G1646B-HCK0
A_RVREF4
		M8			A0
			VREFCA
A_RVREF1					A1
		H1			A2
			VREFDQ		A3
	1%				A4
R710	240	L8			A5
			ZQ		A6
+1.5V_DDR					A7
		B2			A8
			VDD_1		A9
		D9		A10/AP
			VDD_2
		G7			A11
			VDD_3
		K2
			VDD_4	A12/BC
		K8			A13
			VDD_5
		N1
			VDD_6		A14
		N9			A15
			VDD_7
		R1
			VDD_8
		R9			BA0
			VDD_9
					BA1
		A1			BA2
			VDDQ_1
		A8			CK
			VDDQ_2
		C1
			VDDQ_3		CK
		C9			CKE
			VDDQ_4
		D2
			VDDQ_5
		E9
			VDDQ_6		CS
		F1			ODT
			VDDQ_7
		H2
			VDDQ_8		RAS
		H9
			VDDQ_9		CAS
		J1			WE
			NC_1
		J9
			NC_2	RESET
		L1
			NC_3
		L9
			NC_4		DQSL
					DQSL
		A9

								ARA[0-14]
	ARA[0]		ARA[0-14]							ARA[0]	N3
N3
	ARA[1]									ARA[1]	P7
P7
	ARA[2]									ARA[2]	P3
P3
	ARA[3]									ARA[3]	N2
N2
	ARA[4]									ARA[4]	P8
P8
	ARA[5]									ARA[5]	P2
P2
	ARA[6]									ARA[6]	R8
R8
	ARA[7]									ARA[7]	R2
R2
	ARA[8]									ARA[8]	T8
T8
	ARA[9]									ARA[9]	R3
R3
	ARA[10]									ARA[10] L7
L7
	ARA[11]									ARA[11] R7
R7
	ARA[12]									ARA[12] N7
N7
	ARA[13]								ARA[13]		T3
T3
	ARA[14]								ARA[14]		T7
T7
											M7
M7
											M2
M2									ARBA0
		ARBA0									N8
N8									ARBA1
		ARBA1				ARCLK1					M3
M3		ARBA2			ARCLK0				ARBA2		J7
J7								R714
				R712			100				K7
K7			100				5%
K9		ARCKE	5%						ARCKE		K9
					/ARCLK0	/ARCLK1					L2
L2									/ARCSX
		/ARCS
											K1
K1									ARODT
		ARODT									J3
J3
		/ARRAS							/ARRAS		K3
K3
		/ARCAS							/ARCAS		L3
L3
		/ARWE							/ARWE		T2
T2									ARREST
		ARREST									F3
F3									ARDQS2
		ARDQS0									G3
G3									/ARDQS2
		/ARDQS0									C7
C7									ARDQS3

IC703

K4B4G1646B-HCK0

			A_RVREF2
A0	VREFCA	M8
A1			A_RVREF3
A2		H1
A3	VREFDQ
A4			1%
A5			240
		L8		R716
A6	ZQ
A7				+1.5V_DDR
A8		B2
A9	VDD_1
		D9
A10/AP	VDD_2
		G7
A11	VDD_3
		K2
A12/BC	VDD_4	K8
A13	VDD_5
		N1
A14	VDD_6
		N9
A15	VDD_7
		R1
	VDD_8
BA0		R9
	VDD_9
BA1
BA2		A1
	VDDQ_1
CK		A8
	VDDQ_2
		C1
CK	VDDQ_3
		C9
CKE	VDDQ_4
		D2
	VDDQ_5
		E9
CS	VDDQ_6
		F1
ODT	VDDQ_7
		H2
RAS	VDDQ_8
		H9
CAS	VDDQ_9
WE		J1
	NC_1
		J9
RESET	NC_2
		L1
	NC_3
		L9
	NC_4
DQSL
DQSL
DQSU	VSS_1	A9

+1.5V_DDR
A_RVREF2	C735
R720	0.1uF
1K
1%
R721	C736
1K
1%	0.1uF
+1.5V_DDR
A_RVREF3	C733
R718	0.1uF
1K
1%
R719	C734
1K
1%	0.1uF

+1.5V_DDR
			C707
		C705
		1uF	10uF
			10V
+1.5V_DDR
								C704
	C745		C751	C753	C755	C754	C702
	0.1uF		0.1uF	0.1uF	0.1uF	0.1uF	1uF	10uF
								10V

	VSS_1	DQSU
B3
	VSS_2	DQSU
E1
	VSS_3
G8		DML
	VSS_4
J2		DMU
	VSS_5
J8
	VSS_6
M1		DQL0
	VSS_7
M9		DQL1
	VSS_8
P1		DQL2
	VSS_9
P9		DQL3
	VSS_10
T1		DQL4
	VSS_11
T9		DQL5
	VSS_12
		DQL6
B1		DQL7
	VSSQ_1
B9		DQU0
	VSSQ_2
D1		DQU1
	VSSQ_3
D8		DQU2
	VSSQ_4
E2		DQU3
	VSSQ_5
E8		DQU4
	VSSQ_6
F9		DQU5
	VSSQ_7
G1		DQU6
	VSSQ_8
G9		DQU7
	VSSQ_9

B7	ARDQS1				/ARDQS3	B7
	/ARDQS1					E7
E7					ARDQM2
	ARDQM0			ARDQ[16-23]		D3
D3					ARDQM3
	ARDQM1
			ARDQ[0-7]		ARDQ[16]	E3
E3	ARDQ[0]				ARDQ[17]
	ARDQ[1]					F7
F7
	ARDQ[2]				ARDQ[18]	F2
F2
	ARDQ[3]				ARDQ[19]	F8
F8
	ARDQ[4]				ARDQ[20]	H3
H3
	ARDQ[5]				ARDQ[21]	H8
H8
	ARDQ[6]				ARDQ[22]	G2
G2
	ARDQ[7]			ARDQ[24-31]	ARDQ[23]	H7
H7
		ARDQ[8-15]			ARDQ[24]	D7
D7	ARDQ[8]
	ARDQ[9]				ARDQ[25]	C3
C3
	ARDQ[10]				ARDQ[26]	C8
C8
	ARDQ[11]				ARDQ[27]	C2
C2
	ARDQ[12]				ARDQ[28]	A7
A7
	ARDQ[13]				ARDQ[29]	A2
A2
	ARDQ[14]				ARDQ[30]	B8
B8
	ARDQ[15]				ARDQ[31]	A3
A3

+1.5V_DDR

C701

C718

C720

C722

C726

C728

C703

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

1uF

10uF

10V

+1.5V_DDR

C708

C717

C719

C750

C723

C725

C727

C706

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

1uF

10uF

10V

		B3
DQSU	VSS_2
		E1
DML	VSS_3	G8
	VSS_4
		J2
DMU	VSS_5
		J8
	VSS_6
DQL0		M1
	VSS_7
		M9
DQL1	VSS_8
		P1
DQL2	VSS_9
		P9
DQL3	VSS_10
		T1
DQL4	VSS_11
		T9
DQL5	VSS_12
DQL6
DQL7		B1
	VSSQ_1
DQU0		B9
	VSSQ_2
		D1
DQU1	VSSQ_3
		D8
DQU2	VSSQ_4
		E2
DQU3	VSSQ_5
		E8
DQU4	VSSQ_6
		F9
DQU5	VSSQ_7
		G1
DQU6	VSSQ_8
		G9
DQU7	VSSQ_9

IC701-*1		IC701-*2	IC703-*2	IC701-*3	IC703-*3
	IC703-*1				MT41K128M16JT-125:K
H5TQ4G63AFR-PBC	H5TQ4G63AFR-PBC	MT41K256M16HA-125:E	MT41K256M16HA-125:E	MT41K128M16JT-125:K

	+1.5V_DDR				+1.5V_DDR
						R1
RVREF_A			C746			R2
		R730				R3
		1K	0.1uF			R4
	1%
						R5
		R731				K3
		1K	C747			R6
1%			0.1uF			L8
						M8
						D17
						A19
					TP700	J22
						K22
					TP701
			RVREF_A
						D18
					ARCKE	G8
					ARCLK1	B5
						A5
				/ARCLK1
					ARCLK0	B14
						A14
				/ARCLK0
					ARODT	F13
						E13
					/ARRAS
						G13
					/ARCAS
						G15
					/ARCS
						H18
					/ARWE
					ARREST	G16
					ARBA0	D15
						F9
					ARBA1
						G18
					ARBA2
					/ARCSX	F15
					ARA[14]	D11
					ARA[13]	F16
					ARA[12]	D8
					ARA[11]	E11
					ARA[10]	G9
					ARA[9]	E16
					ARA[8]	F11
					ARA[7]	G17
					ARA[6]	F10
					ARA[5]	E17
					ARA[4]	E10
					ARA[3]	E15
					ARA[2]	F17
					ARA[1]	G10
					ARA[0]	F18
			ARA[0-14]

IC105

LGE2122[A2_M13]

DDRV_1			D12
	ARDQM0
DDRV_2			D14
	ARDQS0
DDRV_3			C14
	ARDQS0
DDRV_4		ARDQ0	B17
			D10
DDRV_5		ARDQ1
			C17
DDRV_6		ARDQ2
			C10
DDRV_7		ARDQ3
			C18
DDRV_8		ARDQ4
			B9
DDRV_9		ARDQ5
			E18
DDRV_10		ARDQ6
			D9
DDRV_11		ARDQ7
			C15
MEMTP	ARDQM1
			A13
MEMTN	ARDQS1
			B13
	ARDQS1
		ARDQ8	B11
			B16
RVREF_A		ARDQ9
			A11
	ARDQ10
			A17
	ARDQ11
			C12
ARCKE	ARDQ12
			A16
	ARDQ13
			C11
ARCLK1	ARDQ14
			C16
ARCLK1	ARDQ15
ARCLK0			A3
	ARDQM2
			D5
ARCLK0	ARDQS2
			C5
	ARDQS2
ARODT	ARDQ16		E7
			B2
ARRAS	ARDQ17
			C8
ARCAS	ARDQ18
			B1
ARCS	ARDQ19
			A9
ARWE	ARDQ20
			C1
	ARDQ21
ARRESET			C9
	ARDQ22
			C3
	ARDQ23
ARBA0			C6
ARBA1
	ARDQM3
ARBA2			A4
	ARDQS3
			B4
	ARDQS3
ARCSX	ARDQ24		A1
			B7
ARA14	ARDQ25		C4
	ARDQ26
			C7
ARA13	ARDQ27
			B3
ARA12	ARDQ28
			A7
ARA11	ARDQ29
			A2
ARA10	ARDQ30
			D7
ARA9	ARDQ31
ARA8
ARA			A20
ARA6	AVDD33_MEMPLL
			H9
ARA5	AVSS33_MEMPLL
ARA4
ARA3
ARA2
ARA1
ARA0

ARDQM0

ARDQS0

/ARDQS0 ARDQ[0-7] ARDQ[0]

ARDQ[1]

ARDQ[2]

ARDQ[3]

ARDQ[4]

ARDQ[5]

ARDQ[6]

ARDQ[7]

ARDQM1

ARDQS1

/ARDQS1 ARDQ[8-15] ARDQ[8]

ARDQ[9]

ARDQ[10]

ARDQ[11]

ARDQ[12]

ARDQ[13]

ARDQ[14]

ARDQ[15]

ARDQM2

ARDQS2

/ARDQS2

ARDQ[16]ARDQ[16-23] ARDQ[17]

ARDQ[18]

ARDQ[19]

ARDQ[20]

ARDQ[21]

ARDQ[22]

ARDQ[23]

ARDQM3

ARDQS3

/ARDQS3 ARDQ[24-31] ARDQ[24]

ARDQ[25]

ARDQ[26]

ARDQ[27]

ARDQ[28]

ARDQ[29]

ARDQ[30]

ARDQ[31]

VDD3V3

C700 0.1uF

IC702

MT41K128M16JT-125:K

	+1.5V_DDR				B_RVREF6
								M8		DDR_256MB_MICRON
B_RVREF5		R702	C709						VREFCA		A0
			0.1uF	B_RVREF5							A1
		1K
	1%							H1			A2
									VREFDQ		A3
		R703					1%				A4
			C710
		1K				R711	240				A5
1%			0.1uF					L8			A6
									ZQ
						+1.5V_DDR
											A7
								B2			A8
	+1.5V_DDR								VDD_1		A9
								D9		A10/AP
									VDD_2
								G7			A11
									VDD_3
B_RVREF6			C711					K2
										A12/BC
		R704							VDD_4
			0.1uF					K8
		1K							VDD_5		A13
	1%							N1
									VDD_6
								N9			NC_5
									VDD_7
		R705						R1
			C712						VDD_8
		1K						R9
1%			0.1uF						VDD_9		BA0
											BA1
								A1			BA2
									VDDQ_1
								A8			CK
									VDDQ_2
								C1
									VDDQ_3		CK
								C9			CKE
									VDDQ_4
								D2
									VDDQ_5
								E9
									VDDQ_6		CS
								F1			ODT
									VDDQ_7
								H2
									VDDQ_8		RAS
								H9
									VDDQ_9		CAS
								J1			WE
									NC_1
								J9
									NC_2	RESET
								L1
									NC_3
								L9
									NC_4
						BRA[14]		T7			DQSL
									NC_6
											DQSL
								A9			DQSU
									VSS_1
								B3
									VSS_2		DQSU
								E1
									VSS_3
								G8			DML
									VSS_4
								J2			DMU
									VSS_5
								J8
									VSS_6
								M1			DQ0
									VSS_7
								M9			DQ1
									VSS_8
								P1			DQ2
									VSS_9
								P9			DQ3
									VSS_10
								T1			DQ4
									VSS_11
								T9			DQ5
									VSS_12
											DQ6
								B1			DQ7
									VSSQ_1
								B9			DQ8
									VSSQ_2
								D1			DQ9
									VSSQ_3
								D8			DQ10
									VSSQ_4
								E2			DQ11
									VSSQ_5
								E8			DQ12
									VSSQ_6
								F9			DQ13
									VSSQ_7
								G1			DQ14
									VSSQ_8
								G9			DQ15
									VSSQ_9

		BRA[0]	BRA[0-14]
N3
P7		BRA[1]
P3		BRA[2]
N2		BRA[3]
P8		BRA[4]
P2		BRA[5]
R8		BRA[6]
R2		BRA[7]
T8		BRA[8]
R3		BRA[9]
L7	BRA[10]
R7	BRA[11]
N7	BRA[12]
T3	BRA[13]
M7		BRA[15]
M2		BRBA0
N8
		BRBA1
M3
		BRBA2					BRCLK0
J7				R713
K7			100
K9		BRCKE	5%				/BRCLK0
L2
		/BRCS
K1
		BRODT
J3
		/BRRAS
K3
		/BRCAS
L3
		/BRWE
T2		BRREST
F3		BRDQS0
G3
		/BRDQS0
C7
		BRDQS1
B7
		/BRDQS1
E7		BRDQM0
D3
		BRDQM1
E3						BRDQ[0-7]
	BRDQ[0]
F7	BRDQ[1]
F2	BRDQ[2]
F8	BRDQ[3]
H3	BRDQ[4]
H8	BRDQ[5]
G2	BRDQ[6]
H7	BRDQ[7]
D7	BRDQ[8]				BRDQ[8-15]
C3	BRDQ[9]
C8	BRDQ[10]
C2	BRDQ[11]
A7	BRDQ[12]
A2	BRDQ[13]
B8	BRDQ[14]
A3	BRDQ[15]

		IC702-*1					IC702-*2
	K4B2G1646E-BCK0					H5TQ2G63DFR-PBC
			DDR_256MB_SS				DDR_256MB_HYNIX
N3	A0		VREFCA	M8	N3	A0		VREFCA	M8
P7					P7
P3	A1				P3	A1
N2	A2		VREFDQ	H1	N2	A2			H1
P8	A3				P8	A3		VREFDQ
P2	A4				P2	A4
R8	A5		ZQ	L8	R8	A5			L8
R2	A6				R2	A6		ZQ
T8	A7				T8	A7
R3	A8		VDD_1	B2	R3	A8			B2
L7	A9			D9	L7	A9		VDD_1	D9
R7	A10/AP		VDD_2	G7	R7	A10/AP		VDD_2	G7
N7	A11		VDD_3	K2	N7	A11		VDD_3	K2
T3	A12/BC		VDD_4	K8	T3	A12/BC		VDD_4	K8
	A13		VDD_5	N1		A13		VDD_5	N1
M7			VDD_6	N9	M7			VDD_6	N9
	NC_5		VDD_7	R1		NC_5		VDD_7	R1
M2			VDD_8	R9	M2			VDD_8	R9
N8	BA0		VDD_9		N8	BA0		VDD_9
M3	BA1				M3	BA1
	BA2		VDDQ_1	A1		BA2		VDDQ_1	A1
J7				A8	J7				A8
K7	CK		VDDQ_2	C1	K7	CK		VDDQ_2	C1
K9	CK		VDDQ_3	C9	K9	CK		VDDQ_3	C9
	CKE		VDDQ_4	D2		CKE		VDDQ_4	D2
L2			VDDQ_5	E9	L2			VDDQ_5	E9
K1	CS		VDDQ_6	F1	K1	CS		VDDQ_6	F1
J3	ODT		VDDQ_7	H2	J3	ODT		VDDQ_7	H2
K3	RAS		VDDQ_8	H9	K3	RAS		VDDQ_8	H9
L3	CAS		VDDQ_9		L3	CAS		VDDQ_9
	WE		NC_1	J1		WE		NC_1	J1
T2				J9	T2				J9
	RESET		NC_2	L1		RESET		NC_2	L1
			NC_3	L9				NC_3	L9
F3			NC_4	T7	F3			NC_4	T7
G3	DQSL		NC_6		G3	DQSL		NC_6
C7	DQSL		VSS_1	A9	C7	DQSL			A9
	DQSU					DQSU		VSS_1
B7				B3	B7				B3
	DQSU		VSS_2	E1		DQSU		VSS_2	E1
E7			VSS_3	G8	E7			VSS_3	G8
D3	DML		VSS_4	J2	D3	DML		VSS_4	J2
	DMU		VSS_5	J8		DMU		VSS_5	J8
E3			VSS_6	M1	E3			VSS_6	M1
F7	DQL0		VSS_7	M9	F7	DQL0		VSS_7	M9
F2	DQL1		VSS_8	P1	F2	DQL1		VSS_8	P1
F8	DQL2		VSS_9	P9	F8	DQL2		VSS_9	P9
H3	DQL3		VSS_10	T1	H3	DQL3		VSS_10	T1
H8	DQL4		VSS_11	T9	H8	DQL4		VSS_11	T9
G2	DQL5		VSS_12		G2	DQL5		VSS_12
H7	DQL6				H7	DQL6
	DQL7		VSSQ_1	B1		DQL7		VSSQ_1	B1
D7				B9	D7				B9
C3	DQU0		VSSQ_2	D1	C3	DQU0		VSSQ_2	D1
C8	DQU1		VSSQ_3	D8	C8	DQU1		VSSQ_3	D8
C2	DQU2		VSSQ_4	E2	C2	DQU2		VSSQ_4	E2
A7	DQU3		VSSQ_5	E8	A7	DQU3		VSSQ_5	E8
A2	DQU4		VSSQ_6	F9	A2	DQU4		VSSQ_6	F9
B8	DQU5		VSSQ_7	G1	B8	DQU5		VSSQ_7	G1
A3	DQU6		VSSQ_8	G9	A3	DQU6		VSSQ_8	G9
	DQU7		VSSQ_9			DQU7		VSSQ_9

IC105

LGE2122[A2_M13]

+1.5V_DDR

RVREF_C

RVREF_C

C741

C2

RVREF_C

BRDQM0

L1

BRDQM0

R726

0.1uF

H2

1K

BRDQS0

BRDQS0

1%

H1

/BRDQS0

BRDQ[0-7]

BRDQS0

J2

E2

R727

BRCLK0

J1

BRCLK0

BRDQ0

N3

BRDQ[1]

/BRCLK0

C742

BRCLK0

BRDQ1

BRDQ[2]

1K

E1

1%

0.1uF

BRDQ2

BRDQ[3]

BRDQ3

N1

D1

BRDQ[4]

BRDQ4

P1

BRDQ[5]

BRDQ5

BRCKE

L6

BRCKE

D2

BRDQ[6]

BRDQ6

N2

BRDQ[7]

BRDQ7

BRODT

E3

BRODT

L4

H3

BRDQM1

/BRRAS

BRRAS

BRDQM1

D3

K1

/BRCAS

BRDQS1

BRCAS

BRDQS1

D4

K2

BRDQ[8-15]

/BRCS

/BRDQS1

BRCS

BRDQS1

N4

BRDQ8

BRDQ[8]

BRBA0

J4

BRBA0

F2

BRDQ[9]

BRDQ9

M6

M3

BRDQ[10]

BRBA1

BRBA1

BRDQ10

E4

F1

BRDQ[11]

BRBA2

BRBA2

BRDQ11

L2

BRDQ[12]

BRDQ12

BRA[0-15]

/BRWE

K4

F3

BRDQ[13]

BRWE

BRDQ13

BRDQ[14]

M4

BRA[15]

J3

BRA15

BRDQ14

G3

BRDQ[15]

BRA[14]

BRDQ15

P4

BRA[13]

BRA14

G5

BRA13

BRA[12]

P6

BRA12

BRA[11]

P5

BRA11

BRA[10]

L5

BRA10

BRA[9]

F4

BRA9

BRA[8]

P3

BRA8

BRA[7]

H4

BRA7

BRA[6]

P2

BRA6

BRA[5]

K6

BRA5

BRA[4]

M5

BRA4

BRA[3]

K5

BRA3

BRA[2]

G6

BRA2

BRA[1]

N5

BRA1

BRA[0]

E5

BRA0

+1.5V_DDR

B19

DDRV_12

C19

DDRV_13

D19

DDRV_14

E19

DDRV_15

F19

DDRV_16

G19

DDRV_17

F5

DDRV_18

H5

DDRV_19

N8

BRRESET

G4

BRREST

DDRV_20

P8

DDRV_21

D13

DDRV_22

E8

DDRV_23

G11

DDRV_24

D20

DDRV_25

E20

DDRV_26

F20

DDRV_27

G20

DDRV_28

R7

DDRV_29

R8

DDRV_30

T5

DDRV_31

T6

DDRV_32

T7

DDRV_33

T8

DDRV_34

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

2011.12.09

DDR ONE SIDE 12

Copyright © 2013 LG Electronics. Inc. All rights reserved.	LGE Internal Use Only
Only for training and service purposes