THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
B-MDQU5
B-MCKE
C1214
0.1uF
B-TMDQU5
C1244
0.1uF
VCC_1.5V_DDR
A-MDQSL
R1219
22
A-TMA12
A-TMA6
B-TMDQL5
A-MDQL4
B-TMA10
A-MDQSUB
B-MA10
B-MDML
A-MDQU0
B-MDQSL
B-MVREFDQ
B-TMBA1
A-MA4
B-TMDQSL
R1231
10K
C1205
10uF
VCC_1.5V_DDR
A-TMDQSU
B-MDQU6
B-TMDQSLB
A-TMA8
B-TMA5
C1241
0.1uF
B-MDQU2
C1229
0.1uF
A-TMCK
B-TMCK
B-MVREFCA
B-MDQSLB
AR1214
56
A-TMA6
B-MBA0
B-MODT
AR1213
22
VCC_1.5V_DDR
A-TMDQL5
B-TMDQU6
B-MA3
B-TMA11
A-TMDQSLB
A-TMDQSL
B-MA3
C1204
1000pF
A-MA8
B-TMDQSL
B-MDQL5
B-MDMU
A-TMDQU5
B-TMA2
B-TMBA0
B-TMDQL2
B-TMRESETB
R1209
22
A-TMDQU7
A-MDQL0
A-MVREFCA
A-TMDMU
B-TMCKB
B-TMA1
A-MBA2
A-MDQL6
A-TMDQSLB
B-MDQU3
C1207
0.1uF
B-TMDQL1
A-MA10
B-TMBA0
A-MA2
A-TMWEB
B-TMODT
A-MDQU6
R1238
56
R1211
22
A-TMA10
B-MWEB
A-MDQL7
C1233
0.1uF
A-MDQL5
A-MA10
A-TMCKB
A-TMDQL0
C1217
0.1uF
B-MA2
R1216
56
H5TQ1G63BFR-H9C
IC1201
KOR FAB
A0 N3
A1 P7
A2 P3
A3 N2
A4 P8
A5 P2
A6 R8
A7 R2
A8 T8
A9 R3
A10/AP L7
A11 R7
A12/BC N7
A13 T3
A15 M7
BA0 M2
BA1 N8
BA2 M3
CK J7
CK K7
CKE K9
CS L2
ODT K1
RAS J3
CAS K3
WE L3
RESET T2
DQSL F3
DQSL G3
DQSU C7
DQSU B7
DML E7
DMU D3
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
DQU0 D7
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
A-MBA0
A-MCASB
A-MA8
A-MCKB
A-TMDQU7
A-TMA13
A-TMA2
B-MA6
C1206
0.1uF
B-MA1
B-MCKE
A-TMDQL0
R1222
22
C1234
0.1uF
B-TMA6
A-TMDQU0
A-MA13
A-TMDQL6
B-MA13
A-TMDQU4
B-TMA13
B-TMDQU6
AR1219
56
A-TMBA2
B-TMDQL0
A-MCKB
A-TMA7
C1222
0.1uF
A-TMDQL1
B-MDQU6
A-MRESETB
A-TMCKB
B-MDMU
A-TMA4
B-TMWEB
A-MDMU
A-MDQU7
B-MA5
A-TMCASB
A-MVREFCA
B-MDQU1
B-MDQU5
B-MDQU0
B-MDQSU
A-MA1
B-TMDQL3
A-MDQU4
B-MCKE
LGE101DC-R-1 [S7R DIVX]
IC101
A_DDR3_A0/DDR2_A13
B8
A_DDR3_A1/DDR2_A8
B9
A_DDR3_A2/DDR2_A9
A8
A_DDR3_A3/DDR2_A1
C21
A_DDR3_A4/DDR2_A2
B10
A_DDR3_A5/DDR2_A10
A22
A_DDR3_A6/DDR2_A4
A10
A_DDR3_A7/DDR2_A3
B22
A_DDR3_A8/DDR2_A6
C9
A_DDR3_A9/DDR2_A12
C23
A_DDR3_A10/DDR2_RASZ
B11
A_DDR3_A11/DDR2_A11
A9
A_DDR3_A12/DDR2_A0
C10
A_DDR3_A13/DDR2_A7
B23
A_DDR3_BA0/DDR2_BA2
B21
A_DDR3_BA1/DDR2_CASZ
A11
A_DDR3_BA2/DDR2_A5
A23
A_DDR3_MCLK/DDR2_MCLK
A12
A_DDR3_MCLKZ/DDR2_MCLKZ
C11
A_DDR3_CKE/DDR2_DQ5
B12
A_DDR3_ODT/DDR2_ODT
C20
A_DDR3_RASZ/DDR2_WEZ
A20
A_DDR3_CASZ/DDR2_BA1
B20
A_DDR3_WEZ/DDR2_BA0
A21
A_DDR3_RESETB
C22
A_DDR3_DQSL/DDR2_DQS0
C16
A_DDR3_DQSLB/DDR2_DQSB0
B16
A_DDR3_DQSU/DDR2_DQSB1
A16
A_DDR3_DQSUB/DDR2_DQS1
C15
A_DDR3_DML//DDR2_DQ13
A14
A_DDR3_DMU/DDR2_DQ6
B18
A_DDR3_DQL0/DDR2_DQ3
C18
A_DDR3_DQL1/DDR2_DQ7
B13
A_DDR3_DQL2/DDR2_DQ1
A19
A_DDR3_DQL3/DDR2_DQ10
C13
A_DDR3_DQL4/DDR2_DQ4
C19
A_DDR3_DQL5/DDR2_DQ0
A13
A_DDR3_DQL6/DDR2_CKE
B19
A_DDR3_DQL7/DDR2_DQ2
C12
A_DDR3_DQU0/DDR2_DQ15
A15
A_DDR3_DQU1/DDR2_DQ9
A17
A_DDR3_DQU2/DDR2_DQ8
B14
A_DDR3_DQU3/DDR2_DQ11
C17
A_DDR3_DQU4/DDR2_DQM1
B15
A_DDR3_DQU5/DDR2_DQ12
A18
A_DDR3_DQU6/DDR2_DQM0
C14
A_DDR3_DQU7/DDR2_DQ14
B17
B_DDR3_A0/DDR2_A13 A25
B_DDR3_A1/DDR2_A8 B24
B_DDR3_A2/DDR2_A9 A24
B_DDR3_A3/DDR2_A1 P25
B_DDR3_A4/DDR2_A2 C24
B_DDR3_A5/DDR2_A10 P26
B_DDR3_A6/DDR2_A4 B26
B_DDR3_A7/DDR2_A3 R24
B_DDR3_A8/DDR2_A6 B25
B_DDR3_A9/DDR2_A12 T26
B_DDR3_A10/DDR2_RASZ D24
B_DDR3_A11/DDR2_A11 A26
B_DDR3_A12/DDR2_A0 C25
B_DDR3_A13/DDR2_A7 T25
B_DDR3_BA0/DDR2_BA2 P24
B_DDR3_BA1/DDR2_CASZ C26
B_DDR3_BA2/DDR2_A5 R26
B_DDR3_MCLK/DDR2_MCLK D26
B_DDR3_MCLKZ/DDR2_MCLKZ D25
B_DDR3_CKE/DDR2_DQ5 E24
B_DDR3_ODT/DDR2_ODT N25
B_DDR3_RASZ/DDR2_WEZ M26
B_DDR3_CASZ/DDR2_BA1 N24
B_DDR3_WEZ/DDR2_BA0 N26
B_DDR3_RESETB R25
B_DDR3_DQSL/DDR2_DQS0 J25
B_DDR3_DQSLB/DDR2_DQSB0 J24
B_DDR3_DQSU/DDR2_DQSB1 H26
B_DDR3_DQSUB/DDR2_DQS1 H25
B_DDR3_DML/DDR2_DQ13 F26
B_DDR3_DMU/DDR2_DQ6 L24
B_DDR3_DQL0/DDR2_DQ3 L25
B_DDR3_DQL1/DDR2_DQ7 F24
B_DDR3_DQL2/DDR2_DQ1 L26
B_DDR3_DQL3/DDR2_DQ10 F25
B_DDR3_DQL4/DDR2_DQ4 M25
B_DDR3_DQL5/DDR2_DQ0 E26
B_DDR3_DQL6/DDR2_CKE M24
B_DDR3_DQL7/DDR2_DQ2 E25
B_DDR3_DQU0/DDR2_DQ15 G26
B_DDR3_DQU1/DDR2_DQ9 J26
B_DDR3_DQU2/DDR2_DQ8 G24
B_DDR3_DQU3/DDR2_DQ11 K25
B_DDR3_DQU4/DDR2_DQM1 H24
B_DDR3_DQU5/DDR2_DQ12 K26
B_DDR3_DQU6/DDR2_DQM0 G25
B_DDR3_DQU7/DDR2_DQ14 K24
B-TMWEB
A-MCKE
A-MDQU5
B-TMA7
B-MBA2
A-TMA2
B-MWEB
B-MA8
A-MBA1
VCC_1.5V_DDR
A-MDQSLB
A-MA5
B-TMDQU4
A-MWEB
A-TMA8
C1248
0.1uF
A-TMDMU
B-TMBA1
H5TQ1G63BFR-H9C-C
IC1201-*1
CHN FAB A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
A-TMA12
B-TMDQU2
A-TMDQL2
B-TMA2
B-TMDQU4
A-TMDQU2
A-TMA0
AR1207
22
B-TMCKB
AR1217
22
B-MRASB
A-TMA3
C1219
0.1uF
A-TMRASB
B-MDQSL
B-TMCASB
B-MDQU4
A-MDQL0
C1201
0.1uF
B-TMDQU0
B-MCASB
R1226
240
1%
A-MDQU4
A-TMRESETB
B-MDML
A-TMRESETB
B-MA4
B-MRESETB
VCC_1.5V_DDR
B-MODT
A-MDQU3
A-MA6
AR1205
22
B-MRASB
AR1218
22
C1250
0.1uF
R1213
56
B-MDQU7
A-MDQSL
C1232
0.1uF
B-MDQU2
B-TMDQL4
A-MA12
A-TMDQU3
A-TMA1
B-TMA12
A-TMDQU1
A-MDQL7
B-TMA0
A-TMDQSUB
R1236
56
B-MDQL7
B-MDQSUB
B-MBA1
B-TMRESETB
B-TMDQU1
B-TMCKE
A-MA13
AR1209
22
A-MA3
A-MDML
B-TMBA2
B-MCKB
A-TMA1
A-MA7
C1224
0.1uF
B-MCK
B-TMDQL0
AR1206
22
A-MODT
A-MDQSU
VCC_1.5V_DDR
A-TMBA2
A-MDQL2
B-TMDQL4
B-MCK
B-TMA3
B-MDQL1
B-MDQU4
B-TMA11
B-MDQL6
A-TMCKE
A-TMODT
B-TMDQSLB
A-TMBA0
C1236
0.1uF
B-MA8
B-MDQL6
B-MDQL5
AR1201
56
C1203
0.1uF
B-MDQU7
A-MDQU2
B-TMA6
C1235
0.1uF
C1221
0.1uF
B-TMA13
B-TMDQU0
B-TMDQU3
A-MA0
A-MDQU6
R123410K
B-MA0
AR1211
56
B-TMA7
A-TMA3
R1233 10K
VCC_1.5V_DDR
B-MBA0
A-MDQL2
B-MDQL3
A-MDQU2
A-TMA13
C1209
0.01uF
A-MA7
B-TMDQU2
C1231
0.1uF
A-TMDQU3
A-TMCK
A-MDQU3
B-MCASB
C1226
0.1uF
16V
B-MBA2
B-TMA0
C1210
0.1uF
VCC_1.5V_DDR
B-MDQSUB
B-TMDMU
B-MA2
R1202
1K 1%
B-MDQSU
B-MDQL2
A-MDQSUB
A-TMDQL4
B-TMDQSU
B-TMA9
A-MVREFDQ
VCC_1.5V_DDR
A-MDML
B-MA10
R1227
1K 1%
B-TMDMU
AR1202
56
A-MA12
A-TMCKE
A-MDQU1
A-MDQU5
C1223
0.1uF
R1215
56
B-TMA1
A-MBA0
R1207
22
B-TMDQL2
L1201
A-TMBA1
R1205
1K 1%
A-TMDQU1
A-TMDQL4
A-TMA7
B-TMA12
A-MBA1
B-MVREFCA
R1223
22
B-MA6
B-MA12
A-TMDQSL
C1202
1000pF
C1215
0.1uF
AR1215
56
A-MA4
A-MRASB
AR1204
56
A-MA6
A-TMA0
AR1212
22
B-MDQL3
B-MA0
B-MA1
R1204
1K 1%
AR1208
56
C1245
0.1uF
A-MDQL1
B-TMDQL1
B-MA9
A-TMDQU0
B-TMCKE
C1211
0.1uF
A-MA9 B-TMA4
VCC_1.5V_DDR
A-MRASB
A-TMA11
B-TMDQU1
A-TMA9
A-TMDQU5
AR1210
22
A-TMDQL7
A-TMDQL2
B-TMDML
B-MA7
A-TMDML B-TMDML
A-MDQU1
B-TMDQU7
A-MA3
+1.5V_DDR_IN
A-MCKE
B-TMDQL5
B-MA11
B-TMBA2
B-MDQL0
C1218
0.1uF
C1246
10uF
B-MA12
A-TMDQL5
A-MA5
A-MA11
C1247
1000pF
C1237
0.1uF
A-MDQL6
R1208
22
A-MODT
B-MDQU0
A-TMWEB
A-TMDQU6
B-MDQL7
A-TMDQL6
A-MCK
B-TMA8
A-TMA5
R1218
22
C1242
0.1uF
VCC_1.5V_DDR
B-MVREFDQ
C1208
0.1uF
R1221
22
B-TMA4
A-MCKE
B-TMCK
B-MDQL4
A-MCASB
A-TMDQU2
A-TMODT
B-TMDQSUB
C1230
0.1uF
B-TMDQU3
A-MVREFDQ
A-MA11
H5TQ1G63BFR-H9C-C
IC1202-*1
CHN FAB A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
R1224
1K 1%
B-TMA10
B-MDQL4
R1214
56
B-TMDQL6
A-MDQL3
A-TMDQU6
B-TMA8
B-TMDQL6
A-MA0
R1201
1K 1%
A-TMDML
B-MDQU1
A-TMRASB
B-TMDQU7
B-TMDQSU
A-MDQU0
R1232
10K
B-MA7
A-TMDQU4
R1237
56
A-TMA9
A-TMDQL7
C1216
0.1uF
B-MA13
A-TMA10
B-TMA9
A-TMBA1
A-TMDQL3
R1206
22
A-MDQL3
A-MDMU
A-TMDQSU
A-TMA11
B-TMDQL7
AR1203
56
B-MBA1
B-MDQL0
A-MRESETB
A-MCK
R1210
22
B-TMA5
B-MDQSLB
R1235
56
B-MA11
A-TMDQL3
A-MDQSU
A-TMA4 B-TMA3
B-TMDQL3
A-MA1
C1238
0.1uF
A-MBA2
B-MCKB
A-MDQL4
B-MA4
AR1220
56
A-MDQU7
C1227
0.1uF
A-MDQL1 A-TMDQL1
A-TMA5
B-MDQL2
B-MDQL1
C1220
0.1uF
C1240
0.01uF
AR1216
22
B-TMCASB
B-MA5
B-MA9
B-TMRASB
A-MA2
C1225
10uF
10V
C1212
0.1uF
B-MRESETB
R1220
22
A-MDQSLB
B-MDQU3
R1212
22
C1228
0.1uF
C1213
0.1uF
R1203
240
1%
A-MWEB
C1243
0.1uF
B-TMRASB
R1228
1K 1%
C1239
0.1uF
B-TMDQU5
B-TMDQSUBA-TMDQSUB
A-MA9
B-TMODT
H5TQ1G63BFR-H9C
IC1202
KOR FAB A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
B-TMDQL7
A-TMCASB
R1217
22
A-MDQL5
A-TMBA0
C1249
1000pF
R1225
1K 1%
12 14
DDR
EAX63425902(5)
CLose to Saturn7M IC
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
CLose to Saturn7M IC
CLose to DDR3
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
CLose to DDR3
2010.10.21
Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only