DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock

EXPLANATION OF AC SYMBOLS

In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols.

t

Time

I

Instruction

W

WR signal

A

Address

P

PSEN

X

No longer a valid logic

C

Clock

Q

Output data

 

level

D

Input data

R

RD signal

Z

Tri-State

H

Logic level high

V

Valid

 

 

LLogic level low

POWER-CYCLE TIMING CHARACTERISTICS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

 

 

 

 

 

 

 

Cycle Startup Time

tCSU

 

1.8

 

ms

1

 

 

 

 

 

 

 

Power-On Reset Delay

tPOR

 

 

65,536

tCLCL

2

 

 

 

 

 

 

 

Note 1: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox.

Note 2: Reset delay is a synchronous counter of crystal oscillations after crystal startup. At 33MHz, this time is 1.99ms.

EPROM PROGRAMMING AND VERIFICATION

(VCC = 4.5V to 5.5V, TA = +21°C to +27°C.)

 

 

 

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Programming Voltage

VPP

12.5

 

13.0

V

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Programming Supply Current

IPP

 

 

50

mA

 

Oscillator Frequency

1/tCLCL

4

 

6

MHz

 

Address Setup to

 

 

 

 

 

 

 

Low

tAVGL

48tCLCL

 

 

 

 

PROG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Hold after

 

 

 

 

 

 

 

tGHAX

48tCLCL

 

 

 

 

PROG

 

 

 

 

Data Setup to

 

 

 

 

 

 

 

 

Low

tDVGL

48tCLCL

 

 

 

 

PROG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Hold after

 

 

 

 

 

 

 

 

tGHDX

48tCLCL

 

 

 

 

PROG

 

 

 

 

Enable High to VPP

tEHSH

48tCLCL

 

 

 

 

VPP Setup to

 

 

 

 

 

 

Low

tSHGL

10

 

 

￿s

 

PROG

 

 

 

VPP Hold after

 

 

 

 

 

 

 

 

 

tGHSL

10

 

 

￿s

 

PROG

 

 

 

 

 

 

Width

tGLGH

90

 

110

￿s

 

PROG

 

 

 

 

 

 

 

 

 

 

 

 

Address to Data Valid

tAVQV

 

 

48tCLCL

 

 

Enable Low to Data Valid

tELQV

 

 

48tCLCL

 

 

Data Float after Enable

tEHQZ

0

 

48tCLCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High to

 

 

 

 

 

 

 

Low

tGHGL

10

 

 

￿s

 

 

PROG

PROG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 1: All voltages are referenced to ground.

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