DS87C530/DS83C530 EPROM/ROM Microcontrollers with
MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES (continued)
M2 | M1 | M0 | MOVX CYCLES | tMCS |
0 | 0 | 0 | 2 machine cycles | 0 |
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0 | 0 | 1 | 3 machine cycles (default) | 4 tCLCL |
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0 | 1 | 0 | 4 machine cycles | 8 tCLCL |
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0 | 1 | 1 | 5 machine cycles | 12 tCLCL |
1 | 0 | 0 | 6 machine cycles | 16 tCLCL |
1 | 0 | 1 | 7 machine cycles | 20 tCLCL |
1 | 1 | 0 | 8 machine cycles | 24 tCLCL |
1 | 1 | 1 | 9 machine cycles | 28 tCLCL |
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EXTERNAL CLOCK CHARACTERISTICS
PARAMETER | SYMBOL | MIN | TYP MAX | UNITS |
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Clock High Time | tCHCX | 10 |
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Clock Low Time | tCLCX | 10 |
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Clock Rise Time | tCLCL |
| 5 | ns |
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Clock Fall Time | tCHCL |
| 5 | ns |
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SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS | |
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Serial Port Clock Cycle | tXLXL | SM2 = 0, 12 clocks per cycle | 12tCLCL | ns | |
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Time | SM2 = 1, 4 clocks per cycle | 4tCLCL | |||
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Output Data Setup to | tQVXH | SM2 = 0, 12 clocks per cycle | 10tCLCL | ns | |
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Clock Rising | SM2 = 1, 4 clocks per cycle | 3tCLCL | |||
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Output Data Hold from | tXHQX | SM2 = 0, 12 clocks per cycle | 2tCLCL | ns | |
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Clock Rising | SM2 = 1, 4 clocks per cycle | tCLCL | |||
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Input Data Hold after | tXHDX | SM2 = 0, 12 clocks per cycle | tCLCL | ns | |
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Clock Rising | SM2 = 1, 4 clocks per cycle | tCLCL | |||
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Clock Rising Edge to | tXHDV | SM2 = 0, 12 clocks per cycle | 11tCLCL | ns | |
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Input Data Valid | SM2 = 1, 4 clocks per cycle | 3tCLCL | |||
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