DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock

AC ELECTRICAL CHARACTERISTICS (Note 1)

 

 

 

 

PARAMETER

SYMBOL

33MHz

VARIABLE CLOCK

UNITS

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Oscillator

 

 

 

External Oscillator

1/tCLCL

0

33

0

33

MHz

Frequency

 

 

 

External Crystal

1

33

1

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE Pulse Width

tLHLL

40

 

1.5tCLCL-5

 

ns

Port 0 Address Valid to ALE Low

tAVLL

10

 

0.5tCLCL-5

 

ns

Address Hold after ALE Low

tLLAX1

(Note 2)

 

(Note 2)

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE low to Valid Instruction In

tLLIV

 

43

 

2.5tCLCL-33

ns

ALE Low to

 

 

Low

tLLPL

4

 

0.5tCLCL-11

 

ns

PSEN

 

 

 

 

 

Pulse Width

tPLPH

55

 

2tCLCL-5

 

ns

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low to Valid Instruction In

tPLIV

 

37

 

2tCLCL-24

ns

 

PSEN

 

 

Input Instruction Hold after

 

 

 

 

tPXIX

0

 

0

 

ns

PSEN

 

 

 

 

 

 

 

 

 

 

 

Input Instruction Float after

 

 

 

tPXIZ

 

26

 

tCLCL-5

ns

PSEN

 

 

Port 0 Address to Valid Instruction In

tAVIV1

 

59

 

3tCLCL-32

ns

Port 2 Address to Valid Instruction In

tAVIV2

 

68

 

3.5tCLCL-38

ns

 

 

 

Low to Address Float

tPLAZ

 

(Note 2)

 

(Note 2)

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 1: All parameters apply to both commercial and industrial temperature range operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics are not 100% tested, but are characterized and guaranteed by design. All signals are characterized with load capacitance of 80pF except Port 0, ALE, PSEN, RD and WR with 100pF. Interfacing to memory devices with float times (turn off times) over 25ns may cause contention. This will not damage the parts, but will cause an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle variation.

Note 2: Address is driven strongly until ALE falls, and is then held in a weak latch until overdriven externally.

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