Maxim DS87C530 manual 36

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock

MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES

			PARAMETER				SYMBOL	VARIABLE CLOCK		UNITS	STRETCH
	MIN	MAX
Data Access ALE Pulse Width							tLHLL2	1.5tCLCL-5		ns	tMCS=0
								2tCLCL-5			tMCS>0
Port 0 Address Valid to ALE Low							tAVLL2	0.5tCLCL-5		ns	tMCS=0
								tCLCL-5			tMCS>0
Address Hold After ALE Low for							tLLAX2	0.5tCLCL-10		ns	tMCS=0
MOVX Write								tCLCL-7			tMCS>0
							tRLRH	2tCLCL-5		ns	tMCS=0
RD Pulse Width
								tMCS-10			tMCS>0
							tWLWH	2tCLCL-5		ns	tMCS=0
	WR Pulse Width
								tMCS-10			tMCS>0
							tRLDV		2tCLCL-22	ns	tMCS=0
RD Low Valid Data In
									tMCS-24		tMCS>0
Data Hold After Read							tRHDX	0		ns	—
Data Float After Read							tRHDZ		tCLCL-5	ns	tMCS=0
									2tCLCL-5		tMCS>0
ALE Low to Valid Data In							tLLDV		2.5tCLCL-31	ns	tMCS=0
									tMCS+tCLCL-26		tMCS>0
Port 0 Address to Valid Data In							tAVDV1		3tCLCL-29	ns	tMCS=0
									tMCS+2CLCL-29		tMCS>0
Port 2 Address to Valid Data In							tAVDV2		3.5tCLCL-37	ns	tMCS=0
									tMCS+2.5LCL-37		tMCS>0
							tLLWL	0.5tCLCL-10	0.5tCLCL+5	ns	tMCS=0
ALE Low to RD or WR Low
								tCLCL-5	tCLCL+5		tMCS>0
							tAVWL1	tCLCL-9		ns	tMCS=0
Port 0 Address to RD or WR						Low
								2tCLCL-7			tMCS>0
							tAVWL2	1.5tCLCL-17		ns	tMCS=0
Port 2 Address to RD or WR						Low
								2.5tCLCL-16			tMCS>0
Data Valid to					Transition		tQVWX	-6		ns
				WR
Data Hold After Write							tWHQX	tCLCL-5		ns	tMCS=0
								2tCLCL-6			tMCS>0
		Low to Address Float					tRLAZ		(Note 1)	ns
	RD
							tWHLH	-4	10	ns	tMCS=0
RD or WR High to ALE High
								tCLCL-5	tCLCL+5		tMCS>0

Note 1: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection.

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