DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock

 

PIN DESCRIPTION (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN

NAME

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

PLCC

 

TQFP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program Store-Enable Output. This active-low signal is a chip enable for optional

 

 

38

 

31

PSEN

external ROM memory. PSEN provides an active-low pulse and is driven high when

 

 

 

 

 

 

external ROM is not being accessed.

 

 

 

 

 

 

Address Latch-Enable Output. This pin latches the external address LSB from the

 

 

 

 

 

 

multiplexed address/data bus on Port 0. This signal is commonly connected to the

 

 

39

 

32

ALE

latch enable of an external 373 family transparent latch. ALE has a pulse width of

 

 

 

1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the

 

 

 

 

 

 

device is in a Reset condition. ALE can be disabled and forced high by writing

 

 

 

 

 

 

ALEOFF = 1 (PMR.2). ALE operates independently of ALEOFF during external

 

 

 

 

 

 

memory accesses.

 

 

 

50

 

43

P0.0 (AD0)

 

 

 

 

 

 

 

 

 

 

 

 

49

 

42

P0.1 (AD1)

Port 0 (AD0–AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an

 

 

 

 

 

 

alternate function Port 0 can function as the multiplexed address/data bus to access

 

 

48

 

41

P0.2 (AD2)

 

 

 

off-chip memory. During the time when ALE is high, the LSB of a memory address

 

 

 

 

 

 

 

 

47

 

40

P0.3 (AD3)

 

 

 

is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data

 

 

46

 

39

P0.4 (AD4)

bus. This bus is used to read external ROM and read/ write external RAM memory

 

 

 

 

 

 

or peripherals. When used as a memory bus, the port provides active high drivers.

 

 

45

 

38

P0.5 (AD5)

 

 

 

The reset condition of Port 0 is tri-state. Pullup resistors are required when using

 

 

 

 

 

 

 

 

44

 

37

P0.6 (AD6)

Port 0 as an I/O port.

 

 

 

 

 

 

 

 

 

 

 

 

43

 

36

P0.7 (AD7)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

48

P1.0

Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate

 

 

 

 

 

 

 

 

4

 

49

P1.1

functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1.

 

 

 

The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pullup

 

 

 

 

 

 

holds the port high. This condition also serves as an input mode, since any external

 

 

5

 

50

P1.2

circuit that writes to the port will overcome the weak pullup. When software writes a

 

 

 

0 to any port pin, the device will activate a strong pulldown that remains on until

 

 

 

 

 

 

either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will

 

 

 

 

 

 

 

 

6

 

51

P1.3

cause a strong transition driver to turn on, followed by a weaker sustaining pullup.

 

 

 

Once the momentary strong driver turns off, the port again becomes the output high

 

 

 

 

 

 

 

 

 

 

 

 

(and input) state. The alternate modes of Port 1 are outlined as follows.

 

 

7

 

52

P1.4

 

 

 

Port

Alternate

Function

 

 

 

 

 

 

 

 

 

 

 

 

P1.0

T2

External I/O for Timer/Counter 2

 

 

8

 

4

P1.5

P1.1

T2EX

Timer/Counter 2 Capture/Reload Trigger

 

 

 

 

 

 

P1.2

RXD1

Serial Port 1 Input

 

 

 

 

 

 

P1.3

TXD1

Serial Port 1 Output

 

 

9

 

2

P1.6

 

 

 

P1.4

INT2

External Interrupt 2 (Positive Edge Detect)

 

 

 

 

 

 

P1.5

INT3

External Interrupt 3 (Negative Edge Detect)

 

 

 

 

 

 

 

 

10

 

3

P1.7

P1.6

INT4

External Interrupt 4 (Positive Edge Detect)

 

 

 

P1.7

INT5

External Interrupt 5 (Negative Edge Detect)

 

 

 

 

 

 

 

 

 

 

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