DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
COMPATIBILITY
The DS87C530/DS83C530 are fully static, CMOS 8051-compatible microcontrollers designed for high performance. While remaining familiar to 8051 users, the devices have many new features. In general, software written for existing 8051-based systems works without modification on the DS87C530/DS83C530. The exception is critical timing since the high-speed microcontrollers perform its instructions much faster than the original for any given crystal selection. The DS87C530/DS83C530 run the standard 8051 instruction set. They are not pin compatible with other 8051s due to the timekeeping crystal.
The DS87C530/DS83C530 provide three 16-bit timer/counters, full-duplex serial port (2), 256 bytes of direct RAM plus 1kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051 product. Timers will default to a 12 clock-per-cycle operation to keep their timing compatible with original 8051 systems. However, timers are individually programmable to run at the new 4 clocks per cycle if desired. The PCA is not supported.
The DS87C530/DS83C530 provide several new hardware features implemented by new Special Function Registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW
The DS87C530/DS83C530 feature a high-speed, 8051-compatible core. Higher speed comes not just from increasing the clock frequency, but also from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS87C530/DS83C530, the same machine cycle takes 4 clocks. Thus the fastest instruction, one machine cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions. The majority of instructions on the DS87C530/DS83C530 will see the full 3-to-1 speed improvement. Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of individual programs will depend on the actual instructions used. Speed-sensitive applications would make the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. These architecture improvements produce a peak instruction cycle in 121ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using a table in the High-Speed Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation.
