Motorola DSP56362 specifications BIT Audio Digital Signal Processor

Freescale Semiconductor, Inc.

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SEMICONDUCTOR PRODUCT INFORMATION	DSP56362P/D
	REV. 2
Product Brief	DSP56362
24-BIT AUDIO DIGITAL SIGNAL PROCESSOR

The DSP56362 is a high performance DSP optimized for cost-sensative consumer audio applications. A general purpose DSP56362 is available as well as a multimode, multichannel audio decoder for consumer applications such as Audio/Video (A/V) receivers, surround sound decoders, Digital Versatile Disk (DVD) players, digital TV, and other audio applications. The DSP56362 supports all of the popular multichannel audio decoding formats, including Dolby Digital Surround, Moving Picture Experts Group Standard 2 (MPEG2), and Digital Theater Systems (DTS), in a single device with sufficient MIPS resources for customer defined post-processing features such as bass management, 3D virtual surround, Lucasfilm THX5.1, soundfield processing, and advanced equalization.

The DSP56362, Figure 1,is member of the 56300 Motorola Symphony™ DSP Family. The DSP56362 utilizes the single-instruction-per-clock-cycle DSP56300 core, while retaining code compatibility with the DSP56000 core family. The DSP56362 contains audio-specific peripherals and an on-board software architecture as shown in Figure 2 and is offered in a 100/120 MHz/MIPS version at a nominal 3.3 V.

2

16

12

5

DAX

Host

Program RAM/

X Data

Triple

ESAI

SHI

Instruction

RAM

Y Data

(SPDIF)

Interface

Cache

Timer

5632 ×

24

RAM

Memory

3072 ×

24

ROM

5632 ×

24

Program ROM

Expansion

6144

×

24

ROM

30K ×

24

Area

6144 ×

24

Bootstrap ROM

PIOEB

Peripheral

PMEB

YAB

XMEB

YMEB

Expansion Area

Address

XAB

External

18

Generation

Address

Unit

PAB

Bus

Address

Six Channel

DAB

Switch

DMA

Unit

24-BIT

DRAM/SRAM

DSP56300

Bus

11

Interface

Core

&

Control

I - Cache

Control

DDB

Internal

YDB

External

24

Data

XDB

Data Bus

Bus

PDB

Switch

Data

Switch

GDB

EXTAL

Power

Clock

Mgmt.

Data ALU

6

Generator

Program

Program

Program

Interrupt

Decode

Address

24

× 24 + 56 → 56-bit MAC

JTAG

PLL

Controller

Controller

Generator

Two 56-bit Accumulators

OnCE™

CLKOUT

56-bit Barrel Shifter

MODA/IRQA

MODB/IRQB

RESET

MODC/IRQC

PINIT/NMI

AA0456G

MODD/IRQD

Figure 1 DSP56362 Block Diagram

This document contains information on a new product. Specifications and information herein are subject to change without notice.

DSP56362 Product Brief

©1999 MOTOROLA, INC.

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