Motorola MC68030 specifications 2 0 M H z

A C E L E C T R I C A L S P E C I F I C A T I O N S (Continued)								" {'
Num .			2 0 M H z		2 5 M H z		3 3 . 3 3 M H z		4 0 M H z		5 0 M H z *		Unit
	C h a r a c t e r i s t i c		Min	,Max	M i n	M a x	Min M a x Min M a x Min M a x
17'	A'--S,D~ Negated to R/W Invalid		1Q	- - -	. 7 "	--~	5	- -	3	- -	3	- -	ns
18	Clock High to R / ~ High		O	25	0	20	0	15	O	14	0	14	ns
20	Clock High to R/W Low		0	25	0	20	O	15	0	!4	O	14	ns
21	R/W'High to A T 'Asserted		1 0	- -	7		5	- -	5	- -	3	- -	ns
22	R/W Low to D'--S,~sserted (Write)		60	- -	47	- -	35	- -	24	. - -	23	- -	ns
23	Clock High to Data-Out Valid		- -	2 5	- -	2 0	- -	1 4	- -	1 4	- -	1 4	n s
24	Data-Out Valid to Negating		8	- -	5	- -	3	- -	3	- -	3'	- -	ns
	Edge . of AS ..
2511	AS, DS Negated to Data - Out		10	- -	7	- -	5	- -	3	- -	. 3	- -	ns
	Invalid
25A 9'11	D-S Negated to DBEN Negated		10	- -	7	- -	5	- -	3	- -	3	- -	ns
	(Write)
2611	Data-Out Valid to Asse~ting Edge		10	- -	7	- -	5	- -	3	- -	3	- -	ns
	of DS Asserted	(Write)
27	Data-In Valid to Clock Low		4	- -	2	- -	1	- -	1	- -	1	- -	ns
	(Setup)
27A	Late BERR/HALT Asserted to		10	- -	5	- -	3	- -	3	- -	3	- -	ns
	Clock Low (Setup)
2812	AS, D S N e g a t e d to DSACKx,		O	50	0	40	0	30	0	20	0	15	ns
	BERR, HALT, AVE C
	Negated (Asynchronous Hold)
;)8A17	Clock Low to DSACKx, BERR,		12	85	8	70	6	50	6	40	6	35	ns
	HALT, AVEC Negated
	(Synchronous	Hold)
2912	AS, DS Negated, to Data-In		0	- -	0	- -	0	- -	0	- -	0	- -	ns
	Invalid '(Asynchronous Hold)
29A 12	AS, DS Negated to Data-In		- -	5 0	- -	4 0	- -	3 0	- -	2 5	- -	20	ns
	High Impedance
:3012	Clock Low to Da'ta-lnInvalid		12	- -	8	- -	6	- -	6	- -	6	- -	ns
	(Synchronous	Hold)
30A 12	Clock . Low to.Data-In H i g h .		- -	7 5	- -	6 0	- -	' 4 5 .	- -	3 0 '	- -	2 5	n s
	Impedance (Read followed
	by Write)
31 ~ .	D~ACKx Asserted to Data-In .		- -	4 3	- -	2 8	- -	2 0	- -	1 4	- -	1 3	n s
	Valid (Asynchronous Data.Setup)
31A 3	DSACKx Asserted to DSACKx		- -	1 0	- -	7	- -	5	- -	3	- -	3	n s
	. Valid (Skew)
• :32	RESET input Transition Time "		- -	1,5	. ~	1.5	- -	. 1 . 5,	~	.1.5	- -	1.5	Clks
33	C i o c k L o w to B-G Asserted		0	25	0	20	0	15	0. ,	14	"0	14	ns
34	Clock Low to ~	Negated	0	25	O	20	0	15	0	14	0	14	ns
• .35	BR A s s e r t e d t o BG Asserted		1,5	3,5	1.5	3.5	1.5	3.5	1,5	3.5	1.5	3.5	Clks
	(RMC Not Asserted)

M O T O R O L A M C 6 8 0 3 0 E r E C T R I G A L ; S P E C I E I C A T I O N S 7