AC ELECTRICAL SPECIFICATIONS - - READ A N D WRITE CYCLES•

( V c c . =

5 . 0 V d c

- + 5 % ;

G N D = 0

V d c ;

4 0

M H z - T A

= 0 ° t o

70°C,

5 0

M H z - T A

 

=0° . C t o

T C = 8 0 ° C )

 

 

 

( s e e . . F i g u r e s . 3 - 8 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Num."

 

 

Characteristic

 

 

 

2 0 M H z

 

2 5 M H z

.33.33MHz

 

4 0 M H z

5 0 M H z *

U n i t

 

 

 

 

 

M i n

M a x

 

M i n

 

M a x

M i n

 

M a x

M i n

M a x

M i n

 

 

 

 

 

 

 

 

 

 

 

 

 

M a x • -

6

C!ock'High to Function Code,

 

I,

0

25

 

0

 

20

0

 

14

 

O

14

0

14

ns

 

Size, R M C , IPEND,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOUT, A d d r e s s Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6A

Clock,High

to EC~,

OCS

' ,

 

0

15

 

0

 

i 5

0

 

12

 

0

10

0

10

ns

 

• A s s e r t e d

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

6B '

Functioni~ode,'Size, R M C , '

 

 

4

- -

 

3

 

- -

3

 

- -

'I

3

- -

3

- -

ns

 

IPEND, CLOUT A d d r e s s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Valid to Negating Edge of ECS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

Clock High to Function Code,

 

 

O

50

 

O

 

" 40

O

 

30

 

0

25

0

20

ns

 

Size, RMC, CLOUT,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A d d r e s s

Data

High

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I m p e d a n c e

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.8

Clock High

to Fu'nction Code,

 

 

O

- -

 

0

 

- -

O

 

- -

 

0

- -

0

- -

. ns

 

Size, RMC, IPEND,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOUT, A d d r e s s Invaiid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

Clock L o w

to AS, D'SAsserted,

 

 

3

20

 

3

 

18

2

 

10

2

10

2

10

.ns

 

CBREQ Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9 A 1

AS t o D S

A s s e r t i o n

S k e w

(Read)

 

- 1 0

10"

 

- 1 0

 

10

- 8

 

8

 

: 6

6

- 6

6

ns

9B! 4

A T Asserted to D ~ Asserted

 

 

32

- -

 

27

 

- -

22

 

- -

 

16

- -

14

- - .

ns

 

(Wri.te)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

ECS W i d t h

Asserted

 

 

 

15

- -

 

10

 

- -

8

 

- -

 

5 "

- -

4

- -

ns

"10A

OCS W i d t h Asserted

 

 

 

15

- -

 

10

 

- -

8

 

" - -

 

5

- -

4

- -

ns

1087

ECS, OCS W i d t h

Negated

 

 

 

10

- -

 

5

 

- -

5

 

- -

 

5

- -

4

- -

ns

11

Function

Code,

Size, RMC,

 

 

IO

- -

 

7

 

- -

5 .

 

- -

 

5 "

- -

3

- -

ns

 

CLOUT, A d d r e s s Valid to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asserting Edge of A S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asserted

(arid

DS Asserted,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

Clock L o w

to AS, DS, C e R E Q '

 

 

'O

20

 

O

 

18

' O

 

10

"O . . . .

10"

O

10'

" ns

 

Negated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12A

Clock L o w to ECS/OCS Negated

0

20

 

O

 

18

0

 

15

 

0

12

' 0

11

ns'

13,

AS, DS Negated to Function

 

 

1O

- -

 

7

 

- -

5

 

: - -

 

3

- - ~

3

- -

ns

 

Code,

Size, RMC, CLOUT,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A d d r e s s

Invalid

.

.

.

.

.

.

.

.

.

.

.

.

.

 

 

 

 

 

 

14

AS (and DS Read) W i d t h

 

 

 

85

- -

 

70

 

- -

4 5 ,

 

- - '

 

30

- -

25

- -

ns

'Asserted (Asynchronou's . . . . .

Cycle)

~4A 11

D~

Width Asse'rted(Write)

" '

38

"

~

30

- -

23"

- -

18

m

- 13

7

ns

14B "

AS

(and'DS, Read) Width'

 

35

 

- -

30

- -

23

' - -

"18

- -

13

- -

ns

. .

Asserted ( S y n c h r o n o u s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,15'

AS,

D S W i d t h

Negated

' "

38

 

- -

30

- -

23

- -

1 8

~

. 1 3

- -

. n s

_ .15A8

~

N e g a i e d to

A T Assertecl ..

 

30

 

- -

25

- -

18.

- -

16

. .

:1~'"

- -

ns

16 Clock High to AS, DS, R/W,- - 504030 - - 25 I - - 20 ns

DBEN, CBREQ High I m p e d a n c e

I

 

6

M C 6 8 0 3 0 E L E C T R I C A L ! S P E C I F . I C A T I O N S

M O T O R O L A

Page 8
Image 8
Motorola MC68030 specifications AC Electrical Specifications - Read a N D Write Cycles

MC68030 specifications

The Motorola MC68030 is a highly significant microprocessor that was introduced in 1987 as part of the Motorola 68000 family. This processor was designed to provide advanced performance for a wide range of applications, including workstations, embedded systems, and desktop computers. With its innovative architecture, the MC68030 offered several key features and characteristics that contributed to its popularity.

One of the standout features of the MC68030 is its 32-bit architecture, which enhances data handling and processing efficiency. The processor includes a 32-bit data bus and a 32-bit address bus, allowing it to address up to 4 GB of memory directly. This capability was particularly advantageous for applications requiring large data sets and complex calculations.

The MC68030 introduced an improved memory management unit (MMU), which provided virtual memory support. This advanced memory management enables the CPU to use memory more efficiently by allowing it to access more memory than physically available. The MMU also facilitated advanced features such as memory protection and paging, which were essential for multitasking operating systems.

Another significant advancement in the MC68030 was its integrated cache memory. The processor featured an on-chip instruction cache and an optional data cache, which significantly improved performance by reducing memory access latency. The presence of cache memory allowed for faster instruction execution, enabling the MC68030 to achieve higher overall processing speeds compared to its predecessors.

In terms of instruction set architecture, the MC68030 maintained compatibility with the earlier 68000 series while also introducing new instructions and addressing modes. This ensured that software developed for earlier models could still run on the 68030, protecting the investment of companies that had built their systems around the previous models.

The MC68030 also offered a maximum clock speed of up to 40 MHz, which was quite impressive for its time. This higher clock frequency, coupled with its efficient architectural improvements, allowed the MC68030 to outperform many contemporary processors in both single-task and multi-task scenarios.

In summary, the Motorola MC68030 was a groundbreaking microprocessor that combined 32-bit architecture, advanced memory management, integrated cache, and compatibility with legacy software. Its improved performance and versatility made it a popular choice in various computing environments, from personal computers to sophisticated workstations, leaving a lasting legacy in the evolution of microprocessor technology.