National Instruments GPIB-COM Interrupt Identification Register

Section Five Programming the GPIB-COM

© National Instruments Corporation 5-7 GPIB-COM User Manual

Interrupt Identification Register

Offset from Base I/O Address = 2

Register Address = XFA

7 654 321 0

00

000

ID1 ID0 INT

R

The Interrupt Identification Register is a read-only register which tells you when an interrupt is

pending and if so, what kind of interrupt it is. This register functions identically on the GPIB-

COM and the INS8250.

Bit Mnemonic Description

7-3r 0 Reserved Bits 7 through 3

These bits always read as 0.

2-1r ID[1-0] Identify Interrupt Register Bits

These two bits identify the interrupt that is pending. If more

than one interrupt is pending, only the one with the highest

priority is identified. The types and priorities are given in Table

5-2.

Table 5-2. Interrupt Types and Priorities

Bit 2 Bit 1 Type of Interrupt Priority

0 0 Receiver Line Status 1st

0 1 Received Data Available 2nd

1 0 Transmitter Holding

Register Empty 3rd

1 1 Modem Status 4th

0r INT Interrupt Pending Bit

This bit is clear if an interrupt is pending. If set, no interrupt is

pending.

Contents

Main Page Page FCC/DOC Radio Frequency Interference Compliance Preface Introduction to the GPIB-COM Organization of This Manual Related Documents Abbreviations Used in This Manual Contents Page Figures Tables Section One Introduction GPIB-COM Characteristics What Your Kit Should Contain Optional Equipment Page Page Switch and Jumper Settings Base I/O Address and Interrupt Selection Talk/Listen Modes Talk/Listen Address and Special Function Selection Page Installation Special Considerations When Using the GPIB-COM filename Page Function Description Section Three GPIB-COM User Manual 3-2 National Instruments Corporation Figure 3-1 shows a block diagram of the GPIB-COM. GPIB Figure 3-1. Block Diagram of GPIB-COM GPIB-COM Components Page Section Four Running Diagnostic Tests The GPIB-COM Test Commands -1 printer test -2 plotter test -c change COM configuration -q quit Section Five Programming the GPIB-COM The GPIB-COM Registers Transmitter Holding Register Receive Buffer Register Divisor Latch Least Significant Byte (LSB) Register Divisor Latch Most Significant Byte (MSB) Register Interrupt Enable Register Page Interrupt Identification Register Line Control Register Page Modem Control Register Page Line Status Register Page Modem Status Register Page Programming the Serial Adapter Polling Method Interrupt-Driven Method The GPIB-COM Controller Function Appendix A Specifications Page Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg Message Definitions Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg Appendix C Operation of the GPIB History of the GPIB Types of Messages Talkers, Listeners, and Controllers System Controller and Active Controller GPIB Signals Appendix C Operation of the GPIB National Instruments Corporation C-3 GPIB-COM User Manual Figure C-1 shows the arrangement of these signals on the GPIB cable connector. Data Lines Handshake Lines NRFD (not ready for data) NDAC (not data accepted) Page Page Page Configuration Restrictions User Comment Form