National Instruments GPIB-COM - page 40

Section Five Programming the GPIB-COM

© National Instruments Corporation 5-13 GPIB-COM User Manual

Bit Mnemonic Description

3r FE Framing Error Bit

This bit is set when the received character does not have a valid

stop bit.

On the GPIB-COM, this bit is always clear.

2r PE Parity Error Bit

This bit is set when the received character does not have the

correct parity. It is cleared when the processor reads the Line

Status Register.

On the GPIB-COM, this bit is set when the SRQ* line of the

GPIB is asserted. When the special function selection DIP

switch has been set to disable the SRQ feature, this bit is always

clear.

1r OE Overrun Error Bit

This bit is set when a new character is received and stored in the

Receive Buffer Register before the processor reads the previous

character, thus overwriting and destroying the previous

character. It is cleared when the processor reads the Line Status

Register.

On the GPIB-COM, this bit is always clear.

0r DR Data Ready Bit

This bit is set when a character has been received and stored in

the Receive Buffer Register. It is cleared when the processor

reads the Receive Buffer Register.

This bit functions identically on the GPIB-COM and the

INS8250.

Contents

Main Page Page FCC/DOC Radio Frequency Interference Compliance Preface Introduction to the GPIB-COM Organization of This Manual Related Documents Abbreviations Used in This Manual Contents Page Figures Tables Section One Introduction GPIB-COM Characteristics What Your Kit Should Contain Optional Equipment Page Page Switch and Jumper Settings Base I/O Address and Interrupt Selection Talk/Listen Modes Talk/Listen Address and Special Function Selection Page Installation Special Considerations When Using the GPIB-COM filename Page Function Description Section Three GPIB-COM User Manual 3-2 National Instruments Corporation Figure 3-1 shows a block diagram of the GPIB-COM. GPIB Figure 3-1. Block Diagram of GPIB-COM GPIB-COM Components Page Section Four Running Diagnostic Tests The GPIB-COM Test Commands -1 printer test -2 plotter test -c change COM configuration -q quit Section Five Programming the GPIB-COM The GPIB-COM Registers Transmitter Holding Register Receive Buffer Register Divisor Latch Least Significant Byte (LSB) Register Divisor Latch Most Significant Byte (MSB) Register Interrupt Enable Register Page Interrupt Identification Register Line Control Register Page Modem Control Register Page Line Status Register Page Modem Status Register Page Programming the Serial Adapter Polling Method Interrupt-Driven Method The GPIB-COM Controller Function Appendix A Specifications Page Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg Message Definitions Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg Appendix C Operation of the GPIB History of the GPIB Types of Messages Talkers, Listeners, and Controllers System Controller and Active Controller GPIB Signals Appendix C Operation of the GPIB National Instruments Corporation C-3 GPIB-COM User Manual Figure C-1 shows the arrangement of these signals on the GPIB cable connector. Data Lines Handshake Lines NRFD (not ready for data) NDAC (not data accepted) Page Page Page Configuration Restrictions User Comment Form