National Instruments NI 5422 PFI 0 and PFI 1

NI 5422 Specifications 20 ni.com

PFI 0 and PFI 1

Table 6.

Specification Valu e Comments

Connectors Two SMB (jack) —

Direction Bi-directional —

Frequency

Range

DC to 200 MHz —

As an Input (Trigger)

Destinations Start Trigger —

Maximum

Input Overload

–2 V to +7 V —

VIH 2.0 V —

VIL 0.8 V —

Input

Impedance

1 kΩ—

As an Output (Event)

Sources 1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304)

2. Sample Clock Timebase (200 MHz) divided

by integer M (4 ≤ M ≤ 4,194,304)

3. PLL Reference Clock

4. Marker

5. Exported Start Trigger (Out Start Trigger)

—

Output

Impedance

50 Ω—

Contents

Main NI 5422 Specifications NI PXI-5422 16-Bit 200 MS/s Arbitrary Waveform Generator Contents CH 0 (Channel 0 Analog Output, Front Panel Connector) Page Page Page Figure 1. Normalized Passband Flatness, Direct Path Figure 2. Normalized Passband Flatness, Low-Gain Amplifier Path Figure 3. Normalized Passband Flatness, High-Gain Amplifier Path Figure 4. Pulse Response, Low-Gain Amplifier Path with a 50 Load Page Page Page Average Noise Density specification. Average Noise Density specification. Figure 8. Total Harmonic Distortion, Direct Path Figure 9. Total Harmonic Distortion, Low-Gain Amplifier Path Figure 10. Total Harmonic Distortion, High-Gain Amplifier Path Figure 11. Intermodulation Distortion, 200 kHz Separation (Typical) Sample Clock Page Page Onboard Clock (Internal VCXO) Phase-Locked Loop (PLL) Reference Clock CLK IN (Sample Clock and Reference Clock Input, Front Panel Connector) PFI 0 and PFI 1 (Programmable Function Interface, Front Panel Connectors) Page DIGITAL DATA & CONTROL (DDC) Optional Front Panel Connector Page Start Trigger Markers Page Arbitrary Waveform Generation Mode Page Calibration Power Software Environment NI PXI-5422 Environment Safety, Electromagnetic Compatibility, and CE Compliance Page Physical Where to Go for Support