Operating Precautions for VR4133 TM
(A) Table of Operating Precautions
No. | Outline |
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| µPD30133 |
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| Rev. | 1.1 | 1.2 |
| 1.3 |
| 1.4 | 1.5 | ||
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1 | Simultaneous locking of cache | lines with |
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the same index |
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2 | Reception of non IEEE802.3 conformant |
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3 | Register content in Ether0/1 blocks |
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4 | Read access from external PCI master |
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5 | Write access to external I/O area |
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6 | Branch delay slot of JAL(X) instruction in |
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MIPS16 mode |
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7 | Disconnect at the end of PCI burst cycle |
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8 | Ethernet: receive short packet |
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9 | Ethernet: excessive data transfer into |
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memory |
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10 | Ethernet: transmit short packet |
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11 | Usage PCI and Ether/CEU/BCU/CSI (using |
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12 | Bus arbitration of Internal Bus Arbiter |
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14 | PCI DMA function |
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: Not applicable
: applicable
Note: The rank is indicated by the letter appearing at the 5th position from the left in the lot number, marked on each product.
4 | Customer Notification |