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PC Concepts SHG2 DP Intel Order Number C11343-001 Revision 1.0 , 24, Figure 4. SHG2 Interrupt Routing (PIC Mode)

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Baseboard PCI I/O Subsystem Intel® SHG2 DP Server Board Technical Product Specification

Intel Order Number C11343-001 Revision 1.0 24

CSB5

SCSIi

INTB#

j

S

lot1intB,Slot2intD,Slot3intC,

S

lot4intD,Slot5intC,Slot6intB

1

s

t

LAN 82550

Slot3 intA

Slot6 intA

Slot4 intA

Slot2 intA

SCSIi

INTA#

j

IRQ 0

IRQ 1

IRQ 2

IRQ 3

IRQ 4

IRQ 5

IRQ 6

IRQ 7

IRQ #8

IRQ 9

IRQ 10

IRQ 11

IRQ 12

IRQ 13

IRQ 14

IRQ 15

Timer

Cascade

Connection

Map PCI IR Q to

IRQ[1,3:7, 9:12, 14,15]

SCAN PIRQ

PIRQ 0

PIRQ 1

PIRQ 2

PIRQ 3

PIRQ 4

PIRQ 5

PIRQ 6

PIRQ 7

PIRQ 8

PIRQ 9

PIRQ 10

PIRQ 11

PIRQ12

PIRQ13

PIRQ14

PIRQ 15

PCI Interrupts Address Index Register

PCI Interru pt Redirection Register

IO Address(c00h)

IO Address(c01h)

SCAN IRQ

Keyboard

Serial Port2

Serial Port1

ESMINT

FDD

Parallel Port

RTC

ESMINT

ESMINT

Mouse

FERR#

Super I/O

Slot1 intA

2

n

d

LAN 82544

GA

Slot5 intA

SCI

S

lot1intD,Slot2intC,Slot3intB,

S

lot4intC,Slot5intB

S

lot1intC,Slot2intB,Slot3intD,

S

lot4intB,Slot5intD

PCI

Interrupt

Router

P_IDE

S_IDE

Figure 4. SHG2 Interrupt Routing (PIC Mode)

Contents

Main Revision History Disclaimers Table of Contents CMIC-LE CIOB-X2 2.3.3 2.2.5 Page Page Page Page List of Figures List of Tables Page Page Page Intel SHG2 DP Server Board Technical Product Specification Introduction Revision 1.0 Intel Order Number C11343-001 1 1. Introduction SHG2 Server Board This chapter provides an architectural overview of the Intel CSB5 CIOBX2 1.1 SHG2 Architecture Overview Page 1.2 Document Structure and Outline Page 2. Processor and Chipset 2.1 Overview 2.2 Processor Support 2.2.1 Processor Bus Termination/Regulation/Power 2.2.2 Miscellaneous Processor Subsystem Logic 2.2.3 Server Management Registers and Sensors 2.2.4 ServerWorks* Grand Champion* LE Chipset 2.2.5 CMIC-LE 2.3 Memory Subsystem 2.3.1 Chipkill* 2.3.2 Memory Configuration Page 2.3.3 CIOB-X2 2.4 CSB5 South Bridge 2.4.1 PCI Interface 2.4.2 PCI Bus Master IDE Interface 2.4.3 USB Interface 2.4.4 BIOS Flash 2.4.5 Compatibility Interrupt Control 2.4.7 General Purpose Input and Output Pins 2.5 Chipset Support Components 2.5.1 Legacy I/O (Super I/O) National* PC87417VLA Page Page Page 3. Baseboard PCI I/O Subsystem 3.1 Overview 3.2 64-bit/100MHz PCI-X Subsystem 3.2.1 Device IDs (IDSEL) 3.2.2 64/100MHz PCI-X Arbitration 3.3 64-bit/133MHz PCI-X Subsystem 3.3.1 Device IDs (IDSEL) 3.3.2 64/133MHz Segment Arbitration 3.3.3 Ultra 160 SCSI Controller (Adaptec* AIC- 7899) 3.4 Modular RAID Capable PCI Slot 6 3.5 32-bit/33-MHz PCI Subsystem 3.5.1 Device IDs (IDSEL) 3.5.2 32/33 MHz PCI Arbitration 3.5.3 Network Interface Controller (NIC) 3.5.4 Video Controller 3.6 Interrupt Routing Baseboard PCI I/O Subsystem Intel SHG2 DP Server Board Technical Product Specification Intel Order Number C11343-001 Revision 1.0 24 CSB5 Figure 4. SHG2 Interrupt Routing (PIC Mode) Page 3.6.1 Serialized IRQ support 3.6.2 IRQ scan for PCIIRQ 4. Clock Generation and Distribution Page Intel SHG2 DP Server Board Technical Product Specification Server Management Revision 1.0 Intel Order Number C11343-001 29 5. Server Management Figure 7. SHG2 Sahalee BMC Block Diagram NIC #1 EMP BBD COM2 5.1 Sahalee Baseboard Management Controller 5.2 System Reset Control 5.2.1 Power-up Reset Server Management Intel SHG2 DP Server Board Technical Product Specification Intel Order Number C11343-001 Revision 1.0 32 5.2.2 Hard Reset 5.2.3 Soft Reset Hudson II/III Front Panel 5.3 Intelligent Platform Management Buses Page 6. Error Reporting and Handling 6.1 Error Sources and Types 6.2 Handling and Logging System Errors 6.2.1 Logging Format Conventions Intel Order Number C11343-001 Revision 1.0 The BIOS logs the following SEL entries: Table 26. BIOS Logging SEL List Table 27. Event Request Message Event Data Field Contents 6.3 System Management Interrupt (SMI) Handler 6.3.1 PCI Bus Error 6.3.2 Intel Processor Bus Error 6.3.3 Memory Bus Error 6.4 Firmware (BMC) 6.4.1 System Event Log (SEL) Full 6.4.2 Timestamp Clock 6.4.3 Fault Resilient Booting 6.5 Error Messages and Error Codes 6.5.1 Alert Standard Forum (ASF) Progress Codes 6.5.2 Power-On Self Test (POST) Codes Page Page Page Intel Order Number C11343-001 Revision 1.0 44 Table 31. Recovery BIOS POST Codes 6.5.3 POST Error Codes and Messages Revision 1.0 Intel Order Number C11343-001 45 Table 32. POST Error Messages and Codes 6.5.4 Liquid Crystal Display (LCD) Page 7. Jumpers 7.1 Hardware Configuration Revision 1.0 Intel Order Number C11343-001 49 Table 33. SHG2 Configuration Jumper Options 8. Connections 8.1 Connector Locations The diagram below identifies all the connector locations 8.2 Power Distribution Board Interface Connector CN6 / CN7 / CN4 [Key - M & K & L] Intel Order Number C11343-001 Revision 1.0 Table 37. Power Connector for I 52 C* Bus CN4 [Key-L] 8.3 SCSI Connectors CN54 & CN55 [Key-A & B] Table 38. 68-pin SCSI Connector Pin-out CN54 & CN55 [Key-A & B] Revision 1.0 Intel Order Number C11343-001 53 8.4 Floppy Connector CN31 [Key-H] Table 39 details the pin-out of the 34-pin Legacy floppy connector. Table 39. Legacy 34-pin Floppy Connector Pin-out CN31 [Key-H] 8.5 IDE Connectors CN38 & CN34 [Key-F & G] Table 40 lists the pinout and signal names for the IDE connectors. Revision 1.0 Intel Order Number C11343-001 55 8.6 Front Panel Interface CN37 [Key-E] Table 41. AT Front Panel Header Pinout CN37 [Key-E] Intel Order Number C11343-001 Revision 1.0 56 8.7 Processor Connector CPU1 & CPU2 [Key-J & I] Table 42. Intel Xeon Processor Connector Pinout CPU1 & CPU2 [Key-J & I] Page Page Page 8.8 System Management Interfaces 8.8.1 ICMB Connector 8.8.2 Auxiliary I C* Connector 8.9 Baseboard Fan Connectors (FAN1 through FAN8) Page 8.9.1 Fan Connector Pin-out 8.10 Standard I/O Panel Connectors 8.10.1 Universal Serial Bus (USB) Interface Port B Port A Port C Connections Intel SHG2 DP Server Board Technical Product Specification 8.10.2 Mouse and Keyboard Ports Table 50. Mouse and Keyboard Ports [Key-D & E] Mouse Mouse / Keyboard Connector Keyboard Pin Signal Description Pin Signal Description 8.10.3 Serial Ports 8.10.4 Parallel Port Table 53. Parallel Port Connector [Key-G] Pin Signal Parallel Port Connector Pin Signal 13 1 25 14 Connections Intel SHG2 DP Server Board Technical Product Specification 8.10.5 Video Port Table 54. Video Connector [Key-H] Pin Signal Video Connector Pin Signal 5 1 15 11 6 Page Connections Intel SHG2 DP Server Board Technical Product Specification Intel Order Number C11343-001 Revision 1.0 70 8.11 Connector Manufacturers and Part Number s Table 58. Baseboard Connector Manufacturer Part Numbers Interface Definition Description / Manufacturer Item Number Qty Intel SHG2 DP Server Board Technical Product Specification Connections Interface Definition Description / Manufacturer Item Number Qty 9. General Specifications 9.1 Absolute Maximum Electrical and Thermal Ratings 9.2 Airflow Specification for CIOB-X2 and CMIC-LE 9.3 Electrical Specifications 9.3.1 Power Consumption 9.3.2 Power Supply Specifications Page Page 10. Mechanical Specifications Page 11. Regulatory and Integration Information 11.1 Product Regulatory Compliance 11.1.1 Product Safety Compliance 11.1.2 Product EMC Compliance 11.1.3 Product Regulatory Compliance Markings 11.3 Replacing the Back up Battery Page Intel SHG2 DP Server Board Technical Product Specification Appendix A: Glossary Revision 1.0 Intel Order Number C11343-001 I Appendix A: Glossary Term Definition Appendix A: Glossary Intel SHG2 DP Server Board Technical Product Specification Intel Order Number C11343-001 Revision 1.0 II Appendix B: Reference Documents