Intel® SHG2 DP Server Board Technical Product Specification General Specifications
Revision 1.0 Intel Order Number C11343-001
75
Vout
10% Vout
T
vout rise
T
vout on
T
vout_on
V1
V2
V3
V4
Figure 15. Output Voltage Timing
Table 66 shows the timing requirements for the power supply being turned on and off via the AC input with PSON held low, and the power supply being turned on and off with the PSON signal after AC input is applied.
Table 66. Turn On/Off Timing
Item Description Min Max Units
T
sb_on_delay
Delay from AC being applied to 5VSB being
within regulation. 1500 msec
T
ac_on_delay
Delay from AC being applied to all output
voltages being within regulation. 2500 msec
T
vout_holdup
Time all output voltages stay within regulation
after loss of AC. 21 msec
T
pwok_holdup
Delay from loss of AC to deassertion of
PWOK 20 msec
T
pson_on_delay
Delay from PSON
#
active to output voltages
within regulation limits. 5 400 msec
T
pson_pwok
Delay from PSON
#
deactive to PWOK being
deasserted. 50 msec
T
pwok_on
Delay from output voltages within regulation
limits to PWOK asserted at turn on. 100 1000 msec