Philips AN1651 manual References, NE578, Using the NE/SA5234 amplifier

Philips Semiconductors	Application note
Using the NE/SA5234 amplifier	AN1651

configuration and its output is squared to swing approximately 5V, the standard TTL level. Again common-mode biasing is passed along from each of the stages up to the last in order minimize parts and simplify circuit layout. The final stage is a simple buffer amplifier to allow the receiver to drive a low impedance long wire line of 600Ω to 900Ω resistance. Some rise time response adjustment may be required. This is easily achieved following stage three by using RT-CTto limit the rate of change of the signal voltage prior to the buffer. Note that the last stage acts as a zero-crossing detector. This maximizes noise immunity by allowing a transition only after the third stage output voltage has risen above 2/3VCC. Phase inversion may be accomplished, if the logic level signals are polarity reversed, by making stage 3 inverting and AC coupling the input signal with a sufficiently large capacitor to reduce droop. Stage 3 must then be biased by connecting its non-inverting node to bias point `A'. This provides a 2.5V threshold for the proper

switching operation of the stage. However, care must be taken not allow the network's time constant to become code dependent as to the average low frequency signal components or errors will result in the output signal.

The advantage of this particular circuit is that it has the simplicity of single supply operation along with the capability of a large output swing making it fully TTL compatible

REFERENCES:

Philips Semiconductors. Linear Data Manual, Volume 2 : Industrial.

Sunnyvale: 1988.

Wong, Alvin K. Companding with the NE577 and NE578..Philips Semiconductors Applications Note AN1762 : September 1990.

		C1						10k
	EXPIN						GAINCELL
			+			1	10k
			10μF				ΔG	Σ
					R1*		RECT.	10k
						2		5k
				RECTIN
EXPCAP						3		30k	30k	10k
+
C2	2.2μF
			C3				EXPANDOR
				+		4
	EXPOUT			10μF					Σ
										RECT.
									10k
			C4+
	VREF					5			8.6k

10μF

VREF

6

BANDGAP

10k

Δ

R2*

I

REF

VCC

COMP.

G

PWRDN

GAINCELL

GND MUTE

7

GND

PWRDN/

8

NE578

MUTE

*R1, R2 and R3 are 1% resistors.

16		VCC
15	COMPCAP2
		C8
	+
		2.2μF

C7

14+

10μF COMPIN

13	COMPCAP1
			+C6
12				2.2μF
		RECTIN
		R3*

11GCELLIN

10μF +C5

10 C9 10μFCOMPOUT+

	1nF C11		TO
9		+	PIN 4
	R4		SUMIN
		C10
		10μF

SL00652

Figure 24. Block Diagram of NE578 Test and Application Circuit

1991 Oct 15