Philips DV29 Reset, Zoran Vaddis, Sdram, Flash, Clocks, Front Panel, Digital Audio, Eeprom Memory

FRONT PANEL	RESET
CON202	+3V3D
1

2FPDOUT

3

XFPCLK

IC201

4

XFPSEL

C207

VCC

5

XFPDIN

PWR_ON_RESET*

P239

6

REM_BUS_P

REM_BUS_P

100N

RST

7

IRRCV

GND

9

0603

8

+5V_DISPLAY

16V

10

LM809M3-2.63

11

SOT-23

12

+1V8D

+3V3D

13

REM_BUS_N

OUT -19V

OUT

DGND

14

REM_BUS_N

-9V_OUT -13V5_

_

15

CONFIGURATION LINKS

+3V3D

+3V3D

16

DV75

R203

MOLEX

4K7

52806

DGND

0805

E5 F5 H5 K5 N5 R5 E7 T7 U7 T9 E10 T11 U11 E12 U13 E15 T15 K16 M16 R16 U16

D12 U5

E9 E13 L17 V12 W10 L5

A18 A19 A20

DV79/DV29

R211

P205

6CH*

N3

NVMDA0

VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

VDDP-A VDDP-A

VDDC VDDC VDDC VDDC VDDC VDDC

VDDDAC VDDDAC VDDDAC

R4

NVMDA3

P4

NVMDA1

P3

+3V3D SDRAM decoupling on bottom of board

R3

NVMDA2

4K7

P1

NVMDA4

0805

P2

NVMDA5

C256

C257

C258

C259

C260

C261

C262

N4

NVMDA6

N1

NVMDA7

1N0

1N0

1N0

1N0

1N0

1N0

1N0

DGND

L4

NVMR/B

50V

50V

50V

50V

50V

50V

50V

M3

NVMCE

0603

0603

0603

0603

0603

0603

0603

L3

NVMR/B1

M1

NVMCE1

NVMRE

DGND

N2

NVMWP

M2

NVMWE

DGND

L1

NVMALE

L2

NVMCLE

M4

NVMCD

PCLK

R202

22R

0603

U12

PCLK

RAMCKE

V11

RAMCKE

RAMWE*

Y14

RAMWE

RAMCAS*

W13

RAMCAS

RAMRAS*

Y13

RAMRAS

RAMCS*

Y12

RAMCS

RAMDQM

RAMBA0

W14

RAMDQM

IC202

W11

RAMBA1

RAMBA1

Y11

+3V3D

RAMADD11

U10

RAMBA0

RAMADD11

RAMADD10

W9

RAMADD10

RAMADD9

V10

RAMADD9

43 29 15 1

3 9 35 41 49 55 75 81

RAMADD8

U9

RAMADD8

RAMADD7

V9

RAMADD7

ZORAN VADDIS V

RAMADD5

V8

RAMADD6

VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

RAMADD6

U8

RAMADD4

W7

RAMADD5

R225

PR200

RAMCKE

67

2

RAMDAT0

PR220

RAMADD3

Y7

RAMADD4

CKE

DQ0

RAMADD3

1K0

PR201

PCLK

68

CLK

DQ1

4

RAMDAT1

PR221

RAMADD2

Y8

RAMADD2

0W063

DQ2

5

RAMDAT2

PR222

RAMADD1

W8

RAMADD1

0603

PR202

RAMBA0

22

BA0

DQ3

7

RAMDAT3

PR223

RAMADD0

Y9

RAMADD0

PR253

NF

PR203

RAMBA1

23

BA1

IC203

DQ4

8

RAMDAT4

PR224

RAMDAT0

W18

RAMDAT0

C217

DQ5

11

RAMDAT6

PR226

RAMDAT2

W17

RAMDAT1

10

RAMDAT5

PR225

RAMDAT1

Y18

100N

PR204

RAMWE*

17

DQ6

13

RAMDAT7

PR227

RAMDAT3

Y17

RAMDAT2

WE

DQ7

RAMDAT3

16V

PR205

RAMCAS*

18

CAS

DQ8

74

RAMDAT8

PR228

RAMDAT4

W16

RAMDAT4

0603

PR206

RAMRAS*

19

RAS

DQ9

76

RAMDAT9

PR229

RAMDAT5

Y16

RAMDAT5

HS202

NF

PR207

RAMCS*

20

CS

SDRAM

DQ10

77

RAMDAT10

PR230

RAMDAT6

W15

RAMDAT6

DQ11

79

RAMDAT11

PR231

RAMDAT7

Y15

RAMDAT7

DGND

RAMADD11

21

A11 (NC)

80

RAMDAT12

PR232

+3V3D

RAMDAT8

V14

PR208

RAMADD10

24

DQ12

82

RAMDAT13

PR233

Near ATAPI conn

RAMDAT9

U14

RAMDAT8

SDRAM DECOUPLING

A10/AP

DQ13

RAMDAT9

+3V3D

PR209

RAMADD9

66

83

RAMDAT14

PR234

RAMDAT10

V15

PR210

RAMADD8

65

A9

DQ14

85

RAMDAT15

PR235

RAMDAT11

V16

RAMDAT10

A8

DQ15

C203

C264

C251

RAMDAT11

PR211

RAMADD7

64

A7

DQ16

31

RAMDAT16

PR236

RAMDAT12

V17

RAMDAT12

C212

C213

C214

C215

PR212

RAMADD6

63

A6

DQ17

33

RAMDAT17

PR237

100N

100N

100N

RAMDAT13

U17

RAMDAT13

PR213

RAMADD5

62

A5

IC MEM SDRAM 512KX32BITX4 7NS

DQ18

34

RAMDAT18

PR238

RAMDAT14

V18

RAMDAT14

100N

100N

100N

100N

PR214

RAMADD4

61

A4

DQ19

36

RAMDAT19

PR239

16V

16V

16V

RAMDAT15

U18

RAMDAT15

16V

16V

16V

16V

PR215

RAMADD3

60

A3

DQ20

37

RAMDAT20

PR240

0603

0603

0603

RAMDAT16

W6

RAMDAT16

0603

0603

0603

0603

PR216

RAMADD2

27

A2

DQ21

39

RAMDAT21

PR241

RAMDAT17

Y6

RAMDAT17

PR217

RAMADD1

26

A1

DQ22

40

RAMDAT22

PR242

DGND

RAMDAT18

W5

RAMDAT18

3319B+T410-01

DGND

PR218

RAMADD0

25

A0

DQ23

42

RAMDAT23

PR243

DRIVE

RAMDAT19

Y5

RAMDAT19

20.9C/W

DQ24

45

RAMDAT24

PR244

RAMDAT20

W4

RAMDAT20

47

RAMDAT25

PR245

RAMDAT21

Y4

DQ25

48

RAMDAT26

PR246

RAMDAT22

Y3

RAMDAT21

DQ26

RAMDAT22

PR219

RAMDQM

16

DQM0

DQ27

50

RAMDAT27

PR247

CON203

RAMDAT23

Y2

RAMDAT23

71

DQM1

DQ28

51

RAMDAT28

PR248

1

XATRESET*

RAMDAT24

W2

RAMDAT24

28

DQM2

DQ29

53

RAMDAT29

PR249

2

+5VD

RAMDAT25

W3

RAMDAT25

59

DQM3

DQ30

54

RAMDAT30

PR250

3

ATDD7

RAMDAT26

V4

RAMDAT26

DQ31

56

RAMDAT31

PR251

4

ATDD8

R226

R227

R228

RAMDAT27

U4

RAMDAT27

5

ATDD6

RAMDAT28

V5

RAMDAT28

address

VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

6

ATDD9

0W125

0W125

0W125

RAMDAT29

V6

RAMDAT29

8

ATDD10

RAMDAT31

V7

RAMDAT30

7

ATDD5

1K0

1K0

1K0

RAMDAT30

U6

44 58 72 86

84 78 52 46 38 32 12 6

9

ATDD4

0805

0805

0805

PNVMCE*

Y1

RAMDAT31

PNVMCE

10

ATDD11

PNVMR/B*

W1

PNVMR/B

11

ATDD3

data

12

ATDD12

address

data

13

ATDD2

33R

P243

DGND

14

ATDD13

ATDD0

RP209D

4

5

D2

ATDD0

P244

RAMDAT5

RP200A

1

8 56R

FRAMDAT5

15

ATDD1

ATDD1

RP209C

3

6

33R

C2

ATDD1

P245

RAMDAT6

RP200B

2

7 56R

FRAMDAT6

16

ATDD14

ATDD2

RP209B

2

7

33R

A1

ATDD2

P246

RAMDAT11 RP200C

3

6 56R

FRAMDAT11

17

ATDD0

ATDD3

RP209A

1

8

33R

B2

ATDD3

P247

RAMDAT10 RP200D

4

5 56R

FRAMDAT10

18

ATDD15

ATDD4

RP210D

4

5

33R

D3

ATDD4

P248

19

ATDD5

RP210C

3

6

33R

C3

ATDD5

P249

20

ATDD6

RP210B

2

7

33R

D4

ATDD6

P250

RAMDAT9

RP201A

1

8 56R

FRAMDAT9

21

ATDMARQ

ATDD7

RP210A

1

8

33R

C4

ATDD7

P251

RAMDAT8

RP201B

2

7 56R

FRAMDAT8

22

ATDD8

RP211A

1

8

33R

A4

ATDD8

P252

RAMADD9

RP201C

3

6 56R

FRAMADD9

23

ATDIOW*

ATDD9

RP211B

2

7

33R

B4

ATDD9

P253

RAMADD8

RP201D

4

5 56R

FRAMADD8

24

ATDD10

RP211C

3

6

33R

A3

ATDD10

P254

25

ATDIOR*

ATDD11

RP211D

4

5

33R

B3

ATDD11

P255

26

ATDD12

RP212A

1

8

33R

A2

ATDD12

P256

RAMADD7

RP202A

1

8 56R

FRAMADD7

27

ATIORDY

ATDD13

RP212B

2

7

33R

E4

ATDD13

P257

RAMADD6

RP202B

2

7 56R

FRAMADD6

28

ATDD14

RP212C

3

6

33R

E3

ATDD14

P258

RAMADD5

RP202C

3

6

56R

FRAMADD5

29

ATDMACK*

ATDD15

RP212D

4

5

33R

F4

ATDD15

P259

RAMADD4

RP202D

4

5 56R

FRAMADD4

30

ATDMARQ

R238

82R 0805

B1

ATDMARQ

ATINTRQ

P260

31

ATDIOW*

R241

22R 0805

C1

ATIOW

32

ATDIOR*

R242

22R 0805

P261

D1

RAMADD3

RP203A

1

8 56R

FRAMADD3

33

ATDA1

ATIORDY

R239

82R 0805

P262

F3

ATIOR

ATIORDY

P263

RAMDAT31 RP203B

2

7 56R

FRAMDAT31

34

ATDMACK*

R243

22R 0805

E2

ATDMACK

P264

RAMDAT30 RP203C

3

6 56R

FRAMDAT30

35

ATDA0

ATINTRQ

R240

82R 0805

E1

ATINTRQ

P265

RAMDAT29 RP203D

4

5 56R

FRAMDAT29

36

ATDA2

ATDA0

R244

33R 0805

G3

ATDA0

P266

37

ATCS0*

ATDA1

R245

33R 0805

F1

ATDA1

38

ATCS1*

ATDA2

R246

33R 0805

P267

F2

ATDA2

RAMDAT28 RP204A

1

8

56R

FRAMDAT28

39

ATCS0*

R247

33R 0805

P268

P269

G1

ATCS0

RAMDAT27 RP204B

2

7

56R

FRAMDAT27

Dubilier

40

ATCS1*

R248

33R 0805

G2

ATCS1

ATRESET*

P270

RAMDAT26 RP204C

3

6

56R

FRAMDAT26

C3

XATRESET*

R249

33R 0805

RAMDAT25 RP204D

4

5 56R

FRAMDAT25

DGND

B7

HD0

R250

DDC_SDA

DDC_SDA

A7

HD1

8 56R

B8

HD2

RAMDAT24 RP205A

1

FRAMDAT24

RESET*

A8

5K6

RESET*

+3V3D

HD3

RAMDAT7

RP205B

2

7 56R

FRAMDAT7

B9

HD4

RAMBA0

RP205C

3

6 56R

FRAMBA0

0W125

A9

HD5

RAMBA1

RP205D

4

5 56R

FRAMBA1

0805

B10

HD6

+3V3D

DGND

HDMI_RESET*

HDMI_RESET*

A10

HD7

8 56R

CEC

CEC

B5

HA0

RAMADD10 RP206A

1

FRAMADD10

DDC_SCL

DDC_SCL

A5

HA1

RAMADD0

RP206B

2

7 56R

FRAMADD0

37

47

MUTE_RGB

MUTE_RGB

B6

HA2

RAMADD1

RP206C

3

6 56R

FRAMADD1

PF200

FRAMADD5

25

A0

PROG/INT*

PROG/INT*

A6

HA3

RAMADD2

RP206D

4

5 56R

FRAMADD2

VCC

VCCQ

NOTE: Pin B9 is set HIGH to indicate

C6

HWR

PF202

FRAMADD7

23

A1

D7

HRD

PF201

FRAMADD6

24

D6

RAMDAT16 RP207A

1

8 56R

FRAMDAT16

PF203

FRAMADD8

22

A2

that this version of hardware

C7

HCS

A3

features the HSYNC delay circuit

HIRQ

RAMDAT17 RP207B

2

7 56R

FRAMDAT17

PF204

FRAMADD9

21

A4

DQ0

29

FRAMDAT31

PF216

(see sheet 11)

C5

HACK

RAMDAT18 RP207C

3

6 56R

FRAMDAT18

PF205

FRAMADD11

20

A5

DQ1

31

FRAMDAT29

PF217

D8

HCS1

RAMDAT19 RP207D

4

5 56R

FRAMDAT19

PF206

FRAMDAT8

19

A6

IC205

DQ2

33

FRAMDAT27

PF218

C8

HIRQ1

PF207

FRAMDAT9

18

A7

DQ3

35

FRAMDAT25

PF219

D5

HACK1

FLASH

DQ4

38

FRAMDAT23

PF220

56R

DQ5

40

FRAMDAT21

PF221

DGND

RAMDAT20 RP208A

1

8

FRAMDAT20

PF208

FRAMDAT5

8

A8

42

FRAMDAT19

PF222

C14

XO

RAMDAT21 RP208B

2

7 56R

FRAMDAT21

PF209

FRAMDAT6

7

DQ6

44

FRAMDAT17

PF223

CLK27M_VADDIS

A14

A9

DQ7

CLK27M_VADDIS

GCLKP

RAMDAT22 RP208C

3

6 56R

FRAMDAT22

PF210

FRAMDAT7

6

A10

R219

B15

GCLKA

RAMDAT23 RP208D

4

5

56R

FRAMDAT23

PF211

FRAMBA0

5

A11

DQ8

32

FRAMDAT28

PF225

CLOCKS

0R0

PWR_ON_RESET*

B14

RESET

PF213

FRAMADD10

3

A12

PF212

FRAMBA1

4

30

FRAMDAT30

PF224

GNDP-A2

RAMADD11

PR252

R206

FRAMADD11

PF214

FRAMADD0

2

A13

DQ9

34

FRAMDAT26

PF226

0W125

GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP

GNDC GNDC GNDC GNDC GNDC GNDC

GNDA GNDA

56R

A14

DQ10

Audio master clock (input)

0805

P275

PF215

FRAMADD1

1

A15

DQ11

39

FRAMDAT22

PF239

NF

36

FRAMDAT24

PF227

0W125

0805

DQ12

41

FRAMDAT20

PF240

Can be configured as an output for testing

R224

T5 T6 T8

T10 T12 T13 V13 T14 U15 T16

J9 K9 L9

M9 L10 K11 K12 J11 J12 J10

K10 L11 L12 M10 M11 M12

E8

E14 L16 W12 Y10 M5

A11 A12

H16

DQ13

PF228

FRAMADD2

48

A16

DQ14

43

FRAMDAT18

PF241

MCLK_VADDIS

MCLK_VADDIS

R207

PF229

FRAMDAT10

17

A17

DQ15

45

FRAMDAT16

PF242

0R0

RAMDAT4

FLASHA19

PF230

FRAMDAT11

16

P274 AMCLK_OUT

56R

PF231

FLASHA19

15

A18

R223

0W125

PF232

FRAMDAT3

10

A19

0805

0W125

0805

A20

0R0

PF233

FLASHA21

9

A21

0W125

DGND

PNVMR/B*

PF243

R252

NF(AMD)

PWR_ON_RESET*

12

0805

RP

56R

+3V3D

R210

PF234

FRAMADD4

11

WE

NF

0805

PF235

14

0W125

56R

WP

PF236

PNVMCE*

26

CE

0W125

0805

PF237

FRAMADD3

28

OE

GND GND

+3V3D

RAMDAT3

R208

NF(32Mb+)

FRAMDAT3

R222

PF238

13

VPP

56R

0R0

27 46

0W125

0805

0W125

TE28F160

C253

C252

C223

C225

C227

C229

C231

C232

C233

C234

C235

C236

C237

C238

C239

C240

C249

R253

0805

L967SW

NF

100UF

100UF

100N

100N

100N

100N

100N

100N

100N

100N

100N

100N

100N

100N

100N

100N

100N

RAMDAT4

NF(AMD 16Mb)

FLASHA21

TSOP-48

56R

10V

10V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

0805

DGND

YXF

YXF

0603

0603

0603

0603

0603

0603

0603

0603

0603

0603

0603

0603

0603

0603

0603

0W125

RAMDAT12

R209

NF (Intel 64Mb)

DGND

56R

+3V3D

FLASH DECOUPLING

+3V3D

+1V8D

0W125

0805

C220

C209

C211

C216

C263

C254

C221

C222

C224

C226

C228

C230

C201

C202

100N

100UF

16V

100N

100N

100N

1N0

100N

100N

100N

100N

100N

100N

100N

100N

0603

16V

16V

16V

50V

10V

16V

16V

16V

16V

16V

16V

16V

16V

Use these resistors to configure for

0603

0603

0603

0603

YXF

0603

0603

0603

0603

0603

0603

0603

0603

DGND

Intel/AMD 8Mbit, 16Mbit, 32Mbit or

DGND

DGND

VADDIS DECOUPLING

64Mbit devices

On bottom of board

Intel 32Mbit is used for DV79

To enable Vaddis PLL for testing:

Make PLLCFGA low

Isolate AMCLK from GCLKA

Link GCLKA to GCLKP

Connect AMCLK_OUT to AMCLK

AMCLK is now an output and the Vaddis PLL is

enabled

VDDP_A

P271

L200

120R@100MHz

+3V3D

VDD_PLL

P273

L201

120R@100MHz +1V8D

C208

C210

C248

C250

10UF

100N

10UF

100N

16V

16V

50V

0603

50V

0603

+3V3D

YK

YK

DGND

DGND

A13

G16

A16

VDDA

VDDP-A2

VDDADC

DAC_A_B/U

E17

G17

DAC_D_CVBS

DAC_B_R/V

F17

DAC_C_G/Y

F18

VIDP[0..19]

VIDP[0..19]

DAC_E_Y

G18

+3V3D

H17

DAC_F_C

K17

COSYNC

D16

RSET

D17

C204

C206

VREF

VIDP_0

K19

PV200

RP216A

1

8

100R

VIDP0

PV223

100N

100N

VIDP_1

K20

PV201

RP216B

2

7

100R

VIDP1

PV224

16V

16V

VIDP_2

L19

PV202

RP216C

3

6

100R

VIDP2

PV225

0603

0603

VIDP_3

L20

PV203

RP216D

4

5

100R

VIDP3

PV226

DGND

VIDP_4

L18

PV204

RP217A

1

8

100R

VIDP4

PV227

VIDP_5

M19

PV205

RP217B

2

7

100R

VIDP5

PV228

VIDP_6

M20

PV206

RP217C

3

6

100R

VIDP6

PV229

VIDP_7

M18

PV207

RP217D

4

5

100R

VIDP7

PV230

VIDP_8

M17

PV208

RP218A

1

8

100R

VIDP8

PV231

FRONT PANEL

VIDP_10

N19

PV210

RP218C

3

6

100R

VIDP10

PV233

VIDP_9

N20

PV209

RP218B

2

7

100R

VIDP9

PV232

VIDP_11

N18

PV211

RP218D

4

5

100R

VIDP11

PV234

P200

FPDOUT

VIDP_12

N17

PV212

RP219A

1

8

100R

VIDP12

PV235

VIDP_13

P20

PV213

RP219B

2

7

100R

VIDP13

PV239

C200

VIDP_14

P19

PV214

RP219C

3

6

100R

VIDP14

PV240

VIDP_15

P18

PV215

RP219D

4

5

100R

VIDP15

PV241

47P

VIDP_16

P17

PV216

RP220A

1

8

100R

VIDP16

PV242

100V

VIDP_17

R20

PV217

RP220B

2

7

100R

VIDP17

PV243

IC200A

74HCT125D

0805

VIDP_18

R19

PV218

RP220C

3

6

100R

VIDP18

PV244

DGND

VIDP_19

R18

PV219

RP220D

4

5

100R

VIDP19

PV245

SO-14

P294

R218

2

3

P202

XFPDIN

T19

VCLK

100R

K18

PV220

R200

33R

PV236

CLK_27M_VID

1

VCLKx2

R17

PV221

R201

100R

PV237

0W125

0805

VSYNC

VSYNC*

HSYNC

T20

PV222

R205

100R

PV238

HSYNC*

DGND

E19

DIGITAL AUDIO

AMCLK

DGND

ALRCLKI

E20

P287

RP213A

1

8

56R

AMCLK_OUT

IC200B 74HCT125D

F20

ABCLKI

56R

SO-14

P295

R254

ALRCLKO

F19

P288

RP213B

2

7

ALRCLK

ALRCLK

5

6

P203

XFPCLK

ABCLKO

G19

P289

56R

100R

C17

RP213C

3

6

ABCLK

4

AIN0

C16

ABCLK

0W125

0805

AIN1

J17

P290

RP213D

4

5

56R

ADAT0

AOUT0

ADAT0

J19

P284

3

6

100R

ADAT1

DGND

AOUT1

RP214C

ADAT1

H20

P285

RP214A

1

8

100R

ADAT2

AOUT2

H19

ADAT2

AOUT3

AOUT4

G20

2

7

100R

IC200C 74HCT125D

SPDIF

J20

P286

RP214B

SPDIF

SPDIF

SO-14

P296

R255

FPCDOUT

G4

FPDOUT

9

8

P204

XFPSEL

100R

H4

FPDIN

P291

10

FPCDIN

H3

FPCLK

P292

0W125

0805

FPCCLK

FPCSTB

H1

FPSEL

P293

H2

IRRCV

DGND

IRRCV

W19

MODRI

MODDCD

U20

+5VD

MODDSR

V20

MODCTS

V19

R234

U19

MODDTR

Y20

4K7

MODRTS

Y19

DGND

EEPROM MEMORY

0W125

MODRD

W20

SERIAL PORT

0805

IRRCV

MODTD

IC204A

IRRCV

DUPRD

T3

SERIAL_RX

7

WP

1

+3V3D

C205

U3

DUPTD

SERIAL_TX

6

A0

47P

DGND

2

B13

5

SCL

A1

3

R232

R233

P242

100V

SPIDATI

C13

SDA

A2

4K7

4K7

0805

SPIDATO

D13

DGND

24LC08BT/SN

DGND

0W125

0W125

DGND

SPICLK

B17

SDA

SO-8

0805

0805

I2CDAT

P201

SDA

A17

SCL

P282

I2CCLK

SCL

PWM

C9

SERADC0

C15

+3V3D

B16

DGND

SERADC1

D15

+3V3D

SERADC2

CON201

1

2

3

4

R204

10K

16

EJTAG DEBUG

R237

0W125

RP215A

RP215B

RP215C

RP215D

15

4K7

4K7

4K7

4K7

4K7

0805

14

0W125

62mW

62mW

62mW

62mW

13

K3

EJTRST

0805

8

1206

7

1206

6

1206

5

1206

12

EJTRST

11

EJTDI

K4

EJTDI

10

EJTDO

K2

EJTDO

9

EJTMS

K1

EJTMS

8

J1

EJTCK

PJ203

7

EJTCK

J4

PSUFS0

6

GPCIO6

PSUFS0

5

B18

PSUFS1

4

GPCIO7

C18

ENABLE_AV

PSUFS1

PJ205

3

Not Fitted

GPCIO8

V1

ENABLE_AV

2

GPCIO9

16/9

16/9

PJ200

R251

V2

9190INT*

1

GPCIO10

U2

FSEL1

9190INT*

GPCIO11

FSEL1

33R

U1

GAIN_SCALING

GPCIO12

GAIN_SCALING

0W125

GPCIO13

T1

ML_8740_2

ML_8740_2

0805

HARWIN

T2

MUTE*

DGND

GPCIO14

MUTE*

M20-972

R1

ML_8740_1

GPCIO15

ML_8740_1

R2

ML_8740_0

GPCIO16

ML_8740_0

GPCIO17

B11

MC

MC

NOTE: JTAG port is for software debug only.

C11

MD

GPCIO18

MD

Boundary scan is not supported

C12

ATRESET*

GPCIO19

V3

FSEL0

GPCIO20

FSEL0

GPAIO0

B12

DGND

+3V3D

ATE can use test pad to put in debug boot mode

Fit Link to boot from DEBUG UART

R235

R236

R230

R231

4K7

4K7

0W125

0W125

1K0

1K0

0805

0805

0W125

0W125

BOOTSEL0

C10

0805

P279

0805

BOOT SELECT

D10

BOOTSEL1

D11

P278

BOOTSEL2

CON200

TR200

TESTMODE

D14

1

MMUN2211LT1

IC204B

IC200E

D9

P276

2

SOT-23

24LC08BT/SN

+3V3D

74HCT125D

+5VD

PLLSEL

SO

-8

SO-14

PLLCFGP

J2

P277

HARWIN

VCC

8

VCC

14

J3

M20-973

GNDDAC-SB

PLLCFGA

C218

C219

GNDADC

GNDDAC-P

GNDDAC-D GNDDAC-D GNDDAC-D

0805

0805

0W125

R220

R221

R229

100N

100N

0R0

0R0

GND

4

16V

GND

7

16V

0W125

0W125

1K0

0603

0603

NF

NF

0805

A15

C19

B19

B20

C20

D20

DGND

DGND

ZR36750

BGA-316

IC200D

DGND

74HCT125D

SO-14

Design note: Some Vaddis GPIO

12

11

initialise as o/p high, some as o/p

13

low.

MUTE must use one that initialises

as o/p low. Currently on pin T2

DGND

+3V3D Decoupling caps on bottom of board

C241

C243

C246

C247

1N0	1N0	1N0	1N0
50V	50V	50V	50V
0603	0603	0603	0603
DGND
+1V8D	Decoupling caps on bottom of board

C242 C244 C245 C255

1N0	1N0	1N0	1N0
50V	50V	50V	50V
0603	0603	0603	0603

DGND

DRAWING TITLE DV29 MAIN VADDIS V
￿￿￿￿￿	Filename:	L971C2.sch
	Notes:
A & R Cambridge Ltd.				04_E121	PG	09-08-04	Production release			1.0
Pembroke Avenue
				ECO No.	INITIALS	DATE	DESCRIPTION OF CHANGE			ISSUE
Waterbeach
Cambridge CB5 9QR	Contact Engineer:	Peter Gaggs	Contact Tel: (01223) 203270		Printed:	24-Aug-2004	Sheet 2 of 11	A1	DRAWING NO. L971C2