Philips DRAWING TITLE DV29 VIDEO ENCODER, 0.1% on DV29, 1% on DV79/75, Filename L971C7.Sch

+5V_VID

+3V3D			2	REG700		1				ENC2V5
					+2V5
		C700	7				C717		C702
				SD
							100UF
		100N							100N
				3	ADP3333ARM-2.5
		16V			MSOP-8		10V		16V		Decouple each VDD,VAA & VDD_IO pin with 100n+10n close to pin
	0603						YXF	0603

DGND
		C703	C704	C705	C714	C715	C716
Digital Video Bus VIDP[0..19]	+3V3D	100N	100N	100N	10N	10N	10N
		16V	16V	16V	50V	50V	50V
		0603	0603	0603	0603	0603	0603

C706 C707 C708

P700

R700

560R

0W063

0603

					C709		+5V_VID		D700
									BAT54S SOT-23
					100N
					16V
	L700	P712 L702			0603			IC700A		DGND
				P714	DGND	3	8
										R726
								1	P731
C718			C720	R702		2
	2U2	2U2								75R
6P8	SIMID1210-01 SIMID1210-01		6P8	560R			4	AD8062AR
						P728				0W063
50V			50V	0W063				SO-8
										0603
0603			0603	0603
								Av=2.15
		DGND		R712		R718 DGND
				DGND	1K3	1K5				R727
					0603	0603				75R
										0W063
										0603

P740

COMPOSITE

To Output board

SCART_COMPOSITE

Interlace mode:

C701

C713

VIDP[0..7] = 8 bit Y,Cb,Cr multiplexed data (bit

0 = lsb)

100N

10N

DGND

0.1% for DV29

R740

0.5% for DV79/DV75

Progressive scan mode:

16V

50V

ENC_VREF

0603

0603

VIDP[0..9] = 10 bit multiplexed Cb,Cr data (bit

1K0

REF700

C736

0 = lsb)

0W125

(1.225V)

VIDP[10..19] = 10 bit Y data (bit 10 = lsb)

DGND

1

56

10

41

0805

100N

SOT-23

16V

0603

VIDP[0..19]

VDD IO

VDD VDD

VAA

LM4041AIM3-1.2

VIDP[0..19]

DGND

51

S0

COMP2

36

DGND

52

VIDP0

53

S1

45

VIDP1

54

S2

COMP1

VIDP2

55

S3

46

S4

VREF

VIDP3

58

S5

IC703

VIDP4

59

VIDP5

60

S6

VIDP6

61

S7

ADV7310KST

S8

100N 100N 100N

16V 16V 16V

0603 0603 0603 NF

P701

P702

P707

P711

R701

560R

0W063

0603

	L701	P713	L703		P715
C719	2U2		2U2	C721	R703
6P8	SIMID1210-01		SIMID1210-01	6P8	560R
50V				50V	0W063
0603				0603	0603

		R713
DGND
	DGND	06031K3
		+5V_VID

			+5V_VID			D701
						BAT54S	SOT-23
				IC700B					DGND
		5						R728
						P730
6				7						SVID_Y
				AD8062AR				75R		To Output board
								0W063
				SO-8
	P729						0603
	R719				Av=2.15
		1K5
0603

		VIDP7	62	S9	LQFP-64		44	ENC_COMPOSITE
	HSYNCD*		50			DAC_A
HSYNCD*				S_HSYNC			43	ENC_SVID_Y
	VSYNC*		49
VSYNC*		+3V3D	48	S_VSYNC		DAC_B
				S_BLANK			42	ENC_SVID_C
						DAC_C

P719

+5V_VID	D702
C710	BAT54S SOT-23
100N
16V
0603		DGND

VIDP10

2

Y0

39

ENC_Y/GREEN

VIDP11

3

VIDP12

4

Y1

DAC_D

VIDP13

5

Y2

38

ENC_U/BLUE

Y3

DAC_E

VIDP14

6

VIDP15

7

Y4

37

ENC_V/RED

VIDP16

8

Y5

DAC_F

VIDP17

9

Y6

Y7

VIDP18

12

Y8

VIDP19

13

VIDP0

14

Y9

C0

VIDP1

15

ENC2V5

C1

VIDP2

16

VIDP3

17

C2

VIDP4

18

C3

R736

VIDP5

26

C4

680R

VIDP6

27

C5

0805

VIDP7

28

C6

PLL filter

VIDP8

29

C7

P706

VIDP9

30

C8

23

C9

RSET1

47

P703

C730

C731

24

P_HSYNC

35 P704

820P

3N9

P_VSYNC

RSET2

50V

50V

25

P_BLANK

EXT_LF

34

P705

0603

0603

CLK27M_VID

CLK27M_VID

32

CLKINA

31

63

SDA

CLKINB

RTC_SCR_TR

SDA

DGND

21

SDA

DGND

SCL

SCL

22

SCL

+3V3D

R738

R739

RESET*

RESET*

33

RESET

100R

100R

GND IO

DGND DGND

AGND

I2C

19

0.1%

0.1%

ALSB

20

P709

P710

R737

R721

R722

64

57

11

40

390R

NF

DGND

2K94

2K94

0W063

0.1%

0.1%

P708

0603

C711

DGND

DGND

100N

NF

P718

	P717	R704
		560R
P716
		0W063
		0603

R705

560R

0603

0.1%

0.1% FOR DV29 ELSE 1%

L704

P720

L706

P722

DGND

3

8

IC701A

R729

1

P733

SVID_C

C722

C724

R706

2

2U2

2U2

75R

6P8

SIMID1210-01 SIMID1210-01

6P8

560R

4

AD8062AR

To Output board

0W063

50V

50V

0W063

SO-8

P732

0603

0603

0603

0603

Av=2.15

DGND

R714

R720 DGND

DGND

1K3

1K5

0603

0603

+5V_VID

D703

BAT54S

SOT-23

0.1% FOR DV29

L705

L707

ELSE 1%

IC701B

DGND

P721

P723

5

C723

C725

R707

6

7

P734

2U2

2U2

6P8

SIMID1210-01 SIMID1210-01

6P8

560R

AD8062AR

50V

50V

0603

SO-8

0603

0603

0.1%

P735

Av=2.15

DGND

R715

R723

1K3

1K5

R731

DGND0603 0.1%

0603 0.1%

75R

SCART_GREEN

+5V_VID

0W063

0603

C712

+5V_VID

D704

BAT54S

SOT-23

100N

16V

L708

L710

0603

IC702A

DGND

P724

P726

DGND

3

8

R730		P741
150R		Y
		To Output board
0603	0.1%

R741

150R

0603 0.1%

2 x 150R 0.1% IN PARALLEL FOR DV29 ELSE 1 x 75R 1%

	16V		0.1% on DV29
	0603	Option to parallel terminate clock	1% on DV79/75
DGND

+3V3D

C732 C733 C734 C735

100N	100N	100N	100N
16V	16V	16V	16V
0603	0603	0603	0603

	Around video bus
DGND

R708

560R

0603

0.1%

0.1% FOR DV29 ELSE 1%

R710

560R

0603

0.1%

0.1% FOR DV29 ELSE 1%

1 P737

C726	2U2	2U2	C727	R709	2
6P8	SIMID1210-01 SIMID1210-01		6P8	560R		4	AD8062AR
50V			50V	0603			SO-8
0603			0603	0.1%	P736		Av=2.15
				R716		DGND
		DGND			R724

	1K3	1K5	R733
DGND0603 0.1%		0603 0.1%		SCART_BLUE
0.1% FOR DV29, ELSE 1%			75R
			0W063
			0603

									+5V_VID	D705
										BAT54S SOT-23
										DGND
	L709	P725	L711		P727			5	IC702B
C728				C729	R711			6	7	P738
	2U2		2U2
6P8	SIMID1210-01 SIMID1210-01			6P8	560R				AD8062AR
50V				50V	0603				SO-8
0603				0603	0.1%			P739	Av=2.15
		DGND			R717			R725
					DGND	1K3	0.1%	1K5	0.1%
						0603		0603		R735
					0.1% FOR DV29, ELSE 1%
										SCART_RED
										75R
										0W063
+5VD	L712		+5V_VID							0603
	33U		C754
	1.17A		100UF
	8RHT2
			10V
			YXF
			DGND
Power for video buffers

R732

150R

0603 0.1%

R742

150R

0603 0.1%

R734

150R

0603 0.1%

R743

150R

0603 0.1%

P742

U

To Output board

V

To Output board

DRAWING TITLE DV29 VIDEO ENCODER
￿￿￿￿￿	Filename: L971C7.Sch
	Notes:
A & R Cambridge Ltd.			04_E121	PG	09-08-04	Production release			1.0
Pembroke Avenue
			ECO No.	INITIALS	DATE	DESCRIPTION OF CHANGE			ISSUE
Waterbeach
Cambridge CB5 9PB	Contact Engineer: Peter Gaggs	Contact Tel: (01223) 203270		Printed:	24-Aug-2004	Sheet 7 of 11	DRAWING NO.	L971C7