Troubleshooting
The flash boot loader code is executed every time the CPU is powered or reset. The loader can execute the ISP command handler or the user application code. P0.14 is sensed on a rising edge on the RST (CPU reset) pin. If a low level is detected, ISP command handler starts and takes over control of the CPU after reset. If there is no request for the ISP command handler execution (a
Normally, jumper J25 is set for ‘User mode’ by default.
There was a case, where the code was programmed in the flash, which disabled the JTAG debug port shortly after reset. Due to the NXP implementation, the debugger cannot take over control over the CPU immediately after reset, but a part of code is executed before the CPU can be stopped by the debugger. In this particular case, the application disabled JTAG port before the debugger took control over the CPU and the debugger could not connect to the CPU at all. Thereby, note that if the debugger cannot connect to the CPU (winIDEA reports “Cannot stop CPU”), it may be due to bad program in the flash. In this case,
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© iSYSTEM, March 2007 | 13/13 |
