Philips PNX2000

Product data Rev. 03 – 23 August 2004 21 of 31

Philips Semiconductors PNX2000

Audio video input processor

[1] Allowed SCK/WS ratios are 32, 48, 64, 128 and 256 SCK periods per WS period.

[2] All timings relative to the rising edge of SCK.

[3] See Section 10.4 for waveforms.

th(DATA) data hold at Rx 40 pF load - - 4.9 ns

I2S

fsaudio sample frequency - 32 48 48 kHz

fSCK SCK frequency I2S-bus master mode - 64fs--

fSCK SCK frequency I2S-bus slave mode 32fs64fs256fs-

DFSCK SCK duty factor I2S-bus master mode 40 50 60 %

DFSCK SCK duty factor I2S-bus slave mode 35 - 65 %

tRSCK SCK rise / fa ll time I2S-bus master mode; Cload = 30 pF - - 5 ns

tRSCK SCK rise / fa ll time I2S-bu s slave mode; fSCK = 3.072 MHz - - 50 ns

tddelay time: SCK to WS and SD

outputs [2] TSCK = 1/fSCK 0.3 0.5 0.7 TSCK

thhold time: SCK to WS and SD inputs - 0 - - ns

tssetup time: WS and SD inputs to

SCK TSCK = 1/fSCK 0.2 - - TSCK

I2D

fclock(WORD) word clock frequency - - 13.5 - MHz

WL word length - - 44 - bit

DR data rate - - 594 - Mbit/s

fclock(BIT) bit clock freq. - - 297 - MHz

JTAG Clock Re set

tlow Time RESET_N should be below

Vtrip_high before internal reset = 1. RESET_SEL = 0 - - 11 µs

thigh Time RESET_N should be above

Vtrip_high before internal reset = 0

(after tpulse).

RESET_SEL = 0 - - 2 µs

tpulse Time before PNX2000 internal reset

= 0[3].RESET_SEL = 0 200 - - ns

Table 23: Dynamic characteristics…continued

Symbol Parameter Conditions Min Typ Max Unit