Philips SAA7345 - page 29

1998 Feb 16 29
Philips Semiconductors Product specification
CMOS digital decoding IC with RAM for
Compact Disc SAA7345
I2S timing
CLOCK OUTPUT SCLK (see Fig.23)
tcy output clock period sample rate = fs−472.4 −ns
sample rate = 2fs−236.2 −ns
sample rate = 4fs−118.1 −ns
tHclock HIGH time sample rate = fs166 −−ns
sample rate = 2fs83 −−ns
sample rate = 4fs42 −−ns
tLclock LOW time sample rate = fs166 −−ns
sample rate = 2fs83 −−ns
sample rate = 4fs42 −−ns
tsu set-up time sample rate = fs95 −−ns
sample rate = 2fs48 −−ns
sample rate = 4fs24 −−ns
thhold time sample rate = fs95 −−ns
sample rate = 2fs48 −−ns
sample rate = 4fs24 −−ns
I2S timing (double speed)
CLOCK OUTPUT SCLK (see Fig.23)
tcy output clock period sample rate = fs−236.2 −ns
sample rate = 2fs−118.1 −ns
sample rate = 4fs−59.1 −ns
tHclock HIGH time sample rate = fs83 −−ns
sample rate = 2fs42 −−ns
sample rate = 4fs21 −−ns
tLclock LOW time sample rate = fs83 −−ns
sample rate = 2fs42 −−ns
sample rate = 4fs21 −−ns
tsu set-up time sample rate = fs48 −−ns
sample rate = 2fs24 −−ns
sample rate = 4fs12 −−ns
thhold time sample rate = fs48 −−ns
sample rate = 2fs24 −−ns
sample rate = 4fs12 −−ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT