1998 Feb 16 30
Philips Semiconductors Product specification
CMOS digital decoding IC with RAM for
Compact Disc SAA7345
Notes
1. Timing reference voltage levels are 0.8 V and VDD −0.8 V.
2. Negative set-up time means that data may change after clock transition.
Microcontroller interface timing (see Figs 24 and 25)
INPUTS CL AND RAB
tLinput LOW time single speed 500 −−ns
double speed 260 −−ns
tHinput HIGH time single speed 500 −−ns
double speed 260 −−ns
trrise time single speed −−480 ns
tffall time double speed −−240 ns
READ MODE
tdRD delay time RAB to DA valid 0 −50 ns
tdRZ delay time RAB to DA
high-impedance 0−50 ns
tpd propagation delay CL to DA single speed 700 −980 ns
double speed 340 −500 ns
WRITE MODE
tsuD set-up time DA to CL single speed; note 2 −700 −−ns
double speed; note 2 −340 −−ns
thD hold time CL to DA single speed −−980 ns
double speed −−500 ns
tsuCR set-up time CL to RAB single speed 260 −−ns
double speed 140 −−ns
tdWZ delay time DA high-impedance
to RAB 50 −−ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Fig.23 I2S timing.
DD
V – 0.8 V
0.8 V
DD
V – 0.8 V
0.8 V
tH
MGA376 - 1
tL
clock period tcy
SCLK
WCLK
DATA
MISC
thtsu